Static information storage and retrieval – Powering
Reexamination Certificate
2001-08-13
2002-12-03
Elms, Richard (Department: 2824)
Static information storage and retrieval
Powering
C365S227000, C365S189090, C365S191000, C365S194000, C327S536000, C327S390000, C327S589000, C307S110000
Reexamination Certificate
active
06490220
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a charge pump for generating a larger magnitude output voltage from an input voltage, and more particularly, to a method and apparatus for accurately controlling the boosted voltage generated by a charge pump having multiple cores.
BACKGROUND OF THE INVENTION
Many electronic devices require a plurality of operating voltages. For example, dynamic random access memory (DRAM) devices require a standard operating voltage and an increased voltage. The increased voltage is used, for example, for refreshing. Similarly, some non-volatile memory devices may require an increased voltage for erasing or reprogramming memory cells. Unfortunately, power supplies often only have a limited number of output voltages. Thus, many electronic devices include power conversion circuitry to ensure the availability of required voltages.
One commonly used voltage conversion circuitry is the voltage boosting charge pump. A voltage boosting charge pump is a device which converts an input voltage signal having a level to an output voltage signal having a higher level. Alternatively, a charge pump may accept a negative voltage to produce a more negative voltage signal. Charge pumps are well known in the art and typically include a core which accepts an oscillating clock signal and an input voltage signal. Charge pumps may include multiple cores connected in series to further boost the magnitude of the output voltage signal.
FIG. 1
is a block diagram of a typical multi-core voltage boosting charge pump
1
. The charge pump
1
includes a plurality of charge pump cores
500
a
-
500
d
which are coupled in series. Each charge pump core
500
a
-
500
d
is coupled to a voltage source
101
, and boosts that voltage to a higher value. In addition, the charge pump cores
500
a
-
500
d
are connected in parallel to provide additional current output. Each charge pump core
500
a
-
500
c
is also coupled to a delay chain
400
comprising a plurality of series coupled delay elements
400
a
-
400
d
. The delay chain
400
is used to supply, at different times, an oscillating clock signal from an oscillator
100
to each of the charge pump cores
500
a
-
500
d
via delay taps
401
a
-
401
d
. The final tap
401
d
may be just the output of the final delay element
400
d
. The other taps
401
a
-
401
c
are coupled in parallel to the output of the corresponding delay element
400
a
-
400
c
. The oscillator
100
constantly generates the oscillating clock signal (for example, the signal P illustrated in FIG.
4
A), while a regulator
600
and associated controlled switch
200
determine whether the clock signal reaches the delay chain
400
via a latch
300
.
The oscillator
100
generates an oscillating clock signal P and is coupled to the switch
200
. If the regulator
600
determines that the potential at output node
102
reaches a predetermined voltage, it causes the switch
200
(via signal line
601
) to open, thereby preventing the oscillating clock signal from reaching the charge pump cores
500
a
-
500
d
. However, if the potential at output node
102
is not the predetermined voltage, the regulator
600
causes the switch
200
(also via signal line
601
) to close, thereby permitting the oscillating clock signal to reach a latch
300
. The latch
300
is used to condition the clock signal as it is propagated to delay chain
400
.
The delay chain
400
is comprised of a plurality of delay elements
400
a
-
400
d
coupled in series. The first charge pump core
500
a
is coupled to a voltage source
101
and generates an output voltage signal having a greater potential. Each subsequent charge pump core
500
b
-
500
d
does the same. The parallel connection of the charge pump cores produces additional current on line
102
. Each charge pump core
500
a
-
500
d
generates its output power signal in sequence and at different times, as governed by the delayed pulse train as it passed through differing elements of the delay chain
400
. Additionally, by operating each successive charge pump core at different times, the amount of noise and power drain produced by the multiple core charge pump is reduced.
As noted, the regulator
600
is coupled to the output node
102
and measures node potential. If the potential is at least a threshold level, the regulator
600
controls the switch
200
(via signal line
601
) to decouple the oscillating signal pulses to the delay chain
400
, thereby preventing new pulses of the clock signal P from reaching the charge pump cores
500
a
-
500
d
. However, pulses which are already within the delay chain
400
continue to get tapped at signal lines
401
a
-
401
d
as they propagate through the delay chain. These pulses continue to control the charge pump cores
500
a
-
500
d
, possibly causing the potential at the output node
102
to overshoot beyond a desired value even after the switch
200
has been opened.
SUMMARY OF THE INVENTION
The present invention provides a charge pump circuit and its method of operation which is designed to reduce potential overshoot at the output node when the charge pump is turned off. In one embodiment, the charge pump of the present invention has the oscillator directly coupled to the delay chain. A plurality of switches and associated latches operates in parallel so that a switch/latch pair is located between each tap from the delay chain and a corresponding charge pump core. The control lines for each switch are wired in parallel, so that a regulator may simultaneously open or close the plurality of switches. Since the switches now determine whether the charge pump cores are coupled to the delay chain, the charge pump cores may be more accurately controlled at turn off preventing the potential at the output node from overshooting.
In a modified embodiment, a plurality of transition detectors are provided in series between the taps of the delay chain and the plurality of switches to precondition the clock signals.
REFERENCES:
patent: 6285225 (2002-03-01), Banba et al.
patent: 2001/0017565 (2001-08-01), Zanuccoli et al.
patent: 2001/0026187 (2001-10-01), Oku
Batra Shubneesh
Merritt Todd A.
Elms Richard
Le Toan
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