Method for reliable injection of deterministic jitter for...

Details Method for reliable injection of deterministic jitter for... Method for reliable injection of deterministic jitter for...

2007-09-27

2011-12-06

Tse, Young T. (Department: 2611)

Pulse or digital communications

Testing

Phase error or phase jitter

C375S371000, C713S503000

Reexamination Certificate

active

08073043

ABSTRACT:
A method and a corresponding system for characterizing the performance of a clock and data recovery circuit in a digital transceiver is presented. The method comprises phase modulating a jitter-free data signal by a testing signal having added data jitter and measuring the time the clock and data recovery system takes to achieve bit lock of a phase modulated signal. Data uncorrelated timing jitter corresponding to a user defined probability distribution is included in the jitter testing signal. Utilization of a variable probability distribution in generating data uncorrelated timing jitter, as provided by the present invention, allows for greater flexibility and accuracy in clock and data recovery circuit testing and characterization.

REFERENCES:
patent: 6735160 (2004-05-01), Miyashita et al.
patent: 7388937 (2008-06-01), Rodger et al.
patent: 2006/0100801 (2006-05-01), Tabatabaei et al.
patent: 2006/0291548 (2006-12-01), Mattes et al.
patent: 2010/0026314 (2010-02-01), Schuttert

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