Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-03-25
2004-08-10
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
C438S612000
Reexamination Certificate
active
06773934
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention:
The present invention lies in the field of integrated circuits and relates to a method for releasable contact-connection of a plurality of integrated semiconductor modules on a wafer, the semiconductor modules each having a plurality of interconnected supply voltage terminals.
After their production, semiconductor components are usually subjected to a series of functional tests in order to increase the yield of functional components. For many applications, the most economic procedure for identifying and, if appropriate, also repairing defects is for the procedure to be effected whilst still on the wafer, that is to say, before the modules are separated and housed.
Likewise, a so-called burn-in is often carried out for semiconductor components, in which the components are aged before use in a targeted manner by the manufacturer to reduce the failure rate of the components supplied to the customers to an approximately constant low value compared with the initial failure rate. Here, too, it is desirable if such a burn-in can be carried out simultaneously for as many components as possible at the wafer level.
The drive system used for a module test or for a burn-in is referred to uniformly below as test system, without restricting the generality. The connection between the test system and the components on the wafer is produced by a contacting card, for example, a needle card. In such a case, the majority of the contact-connecting needles serve for transmitting test, data, and control signals from the test system to the module to be tested. Further contact-connecting needles connected to a voltage source carry one or more supply voltages, for example, with a level of 3.3 V or 2.5 V, to corresponding pads of the semiconductor module.
The aim, both in the module test and in the burn-in, is for the components of the largest possible part of the wafer, preferably of the entire wafer, to be contact-connected simultaneously. Due to the large number of components on the wafer and the limited number of system channels available on the test system for driving the components, a parallel circuit of a plurality of components is required for such a purpose. This means that the same electrical signal is provided only once by the test system and applied to corresponding terminals of a plurality of components.
In such a case, however, the problem arises that previous methods for verifying the quality of the contact between contacting card and components no longer yield satisfactory results. In the prior art methods, one channel of the test unit is connected to exactly one component terminal. A current is impressed on the connecting line and the voltage drop across the input protection diodes of the component terminal is measured. If the voltage drop lies in the range around the typical value of 0.6 V, for example, then the contact is identified as defect-free.
In the case of parallel contact-connection of a plurality of components, however, it is no longer possible to see from the measured voltage drop whether or not all of the components driven in parallel have adequate contact because there is no longer an unambiguous assignment between the output signal and the tested component.
European Patent 0733 910 B1, corresponding to U.S. Pat. No. 5,815,001 to Ewald, describes a method for carrying out a contact check of a plurality of integrated circuits mounted on a circuit board, the integrated circuits having not only the basic configuration but also a test configuration that, when test signals are present at first terminals of the circuit, transmits corresponding result signals to second terminals of the circuit.
U.S. Pat. No. 6,100,710 to Monnot discloses a method for checking the contact of an integrated semiconductor circuit with two different ground terminals.
A further method for carrying out a contact check of a plurality of integrated circuits mounted on a circuit board is disclosed in U.S. Pat. No. 5,072,175 to Marek. In Marek, a dedicated test diode is provided for each circuit and for each terminal.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for releasable contact-connection of a plurality of integrated semiconductor modules on a wafer that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that checks releasable contacts on a plurality of integrated semiconductor modules of the type mentioned above and enables reliable checking of the contact quality.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for checking releasable contacts of integrated semiconductor modules on a wafer, the semiconductor modules each having interconnected supply voltage terminals including the steps of connecting the contacts of a semiconductor module on the wafer in parallel with a contacting card, applying a supply voltage to a first one of the supply voltage terminals of the semiconductor module through the contacting card, measuring a voltage present at a second one of the supply voltage terminals of the semiconductor module through the contacting card, comparing the voltage applied to the first supply voltage terminal with the voltage measured at the second supply voltage terminal, and evaluating a contact status for the semiconductor module as being correct if the voltage measured at the second supply voltage terminal substantially corresponds to the voltage applied to the first supply voltage terminal, and otherwise as being incorrect.
The invention is, thus, based on the concept of using the interconnected supply voltage terminals of the semiconductor modules for the contact test by applying to at least one of these terminals a voltage whose presence at another one of the supply voltage terminals serves as verification of a correct contact.
The method of the invention can be realized at any time without appreciable additional technical outlay. The assessment of the contact quality using a single measurement per component is based on the observation that although the quality of contacts can change extensively over the entire wafer, it, nonetheless, scarcely varies locally over the area of an individual component. Therefore, it is highly likely that a poor contact on one component will also appear at the measured supply voltage terminal. Consequently, the proposed contact test provides a good general statement about the quality of the contact-connection and can also be effected independently of a complicated test system beforehand in a separate, simple contact test station.
The assessment of the measurement results for all the checked semiconductor modules is preferably conducted for evaluation to ascertain whether or not there is a correct contact between wafer and contacting card.
In accordance with another mode of the invention, the evaluation of the semiconductor module is indicated with an indication device.
In accordance with a further mode of the invention, the connecting, applying, measuring, comparing, and evaluating steps are repeated for each of the semiconductor modules.
In accordance with an added mode of the invention, the evaluation of the semiconductor modules is simultaneously indicated with an indication device. Preferably, all of the semiconductor modules are simultaneously indicated.
In accordance with an additional mode of the invention, a result of the evaluation for a given semiconductor module is indicated with a representation indicating a position of the respective semiconductor module on the wafer.
In accordance with yet another mode of the invention, a result of the evaluation for all of the semiconductor modules is simultaneously indicated with a representation indicating a position of each respective semiconductor module on the wafer.
In accordance with yet a further mode of the invention, the releasable electrical connection between the terminal pads of the semiconductor modules and the contacting card is formed by intermediate elements disposed on the
Färber Gerrit
Fritz Martin
Hübner Michael
Möckel Jens
Weber Frank
Everhart Caridad
Mayback Gregory L.
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