Method for regulating an output signal and circuit therefor

Details Method for regulating an output signal and circuit therefor Method for regulating an output signal and circuit therefor

2008-07-15

2008-07-15

Nguyen, Matthew V (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S282000

Reexamination Certificate

active

07400127

ABSTRACT:
A regulator circuit and a method for compensating for sag in the output signal of the regulator circuit. A first comparator is coupled to an input of an oscillator, which oscillator outputs a clock signal and a ramp signal. In accordance with a feedback signal from the output of the regulator circuit, the clock and ramp signals of the oscillator are reset if the output signal sags to an undesirable level. The clock and ramp signals can be reset between active edges of the clock. The reset clock and ramp signals cause the regulator circuit to increase its output voltage to reduce the sag.

REFERENCES:
patent: 6057675 (2000-05-01), Tateishi
patent: 6580258 (2003-06-01), Wilcox et al.
patent: 6597221 (2003-07-01), Hall et al.
patent: 6794917 (2004-09-01), Barrow et al.
patent: 6897640 (2005-05-01), Nebon et al.
patent: 2006/0043951 (2006-03-01), Oswald et al.

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