Method for regular placement of data path components in VLSI cir

Details Method for regular placement of data path components in VLSI cir Method for regular placement of data path components in VLSI cir

1991-08-20

1994-10-25

Trans, Vincent N.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

053595386

ABSTRACT:
In a method for placement of components for a VLSI circuit, control signal connection networks and data signal connection networks are identified. Then, an initial placement of the components for the VLSI circuit is made. This initial placement is iteratively improved. The algorithm used for the iterative improvement has a cost metric in which a horizontal component for length of a connection network and a vertical component for length of the connection network are weighted differently dependent on whether the connection network was identified as a control signal connection network or a data signal connection network. The different weighting results in improved regularity of the placement of data path components and thus a more efficient routing of connection networks between the components.

REFERENCES:
patent: 5202840 (1993-04-01), Wong
patent: 5222031 (1993-06-01), Kaida
patent: 5229953 (1993-07-01), Isozaki et al.
"Multi-Terrain Partitionary and Flood-Planning for Data-Path chip (Microprocessor) Layout" by Wing K. Luk et al., IEEE 26th ACM Design Automation Conference, Jun. 1989, pp. 492-494.
C. M. Fiduccia and R. M. Mattheyses, A Linear-Time Heuristic for Improving Network Partitions Proceedings of the 19th Design Automation Conference, 1982, pp. 241-247.
Maurice Hanan, Peter K. Wolff, Sr. and Barbara J. Agule, Some Experimental Results of Placement Techniques, Proceedings of the 13th Design Automation Conf., 1976, pp. 214-224.
Carl Sechen and Alberto Sangiovanni-Vincentelli, The Timber Wolf Placement and Routing Package, IEEE Journal of Solid-State Circuits, 1985, pp. 510-522.
Gotaro Odawara, Takahisa Hiraide, and Osamu Nishina, Partitioning and Placement Technique for CMOS Gate Arrays, IEEE Transactions on Computer-aided Design, 1987, pp. 355-363.

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