Method for redundancy-saving, error-correcting coding in digital

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371 45, G06F 1100

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051154382

ABSTRACT:
For the employment of an FEC method in systems of a variety of types, the serial binary data stream to be transmitted is supplied to a means for rate matching and for serial-to-parallel conversion wherein, first, the data rate is increased to the transmission rate upon formation of free locations for the acceptance of redundancy bits and, second, a corresponding plurality of parallel data streams are generated from the serial data stream, respectively one half of said parallel data streams forming the I-channel and the other half forming the Q-channel. The redundancy locations lie in the least significant bits of the I-channel and Q-channel. The more significant bits of the I-channel and the Q-channel directly control the appertaining inputs of a quadrature modulator, whereas the least significant bit is supplied to the appertaining input via a respective multiplexer. In addition, the least significant bit of the I-channel and the Q-channel is respectively supplied to a coder, each of these coders considering a defined plurality of incoming bits; and generating one or more redundancy bits therefrom in accord with the coding rule of a specific underlaid code. These redundancy bits are inserted with the assistance of the multiplexers at locations in the I-channel and Q-channel, that are provided for this purpose.

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