Method for reducing within chip device parameter variations

Details Method for reducing within chip device parameter variations Method for reducing within chip device parameter variations

2008-07-01

2008-07-01

Thai, Luan (Department: 2891)

Semiconductor device manufacturing: process

With measuring or testing

C438S011000

Reexamination Certificate

active

11382489

ABSTRACT:
A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

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