Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-07-08
2002-07-16
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S734000
Reexamination Certificate
active
06420240
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor device fabrication and more particularly to processes for fabricating shallow trench isolation structures.
2. Description of the Related Art
Shallow trench isolation (“STI”) is a well known semiconductor device fabrication process whereby features of a device are electrically isolated using relatively shallow trenches. STI has several advantages including higher device density by increasing the number of overlying levels on which features of the device are formed.
FIGS. 1A-1F
show cross-sectional views of a flash memory device being fabricated in accordance with a method in the prior art. As shown in
FIG. 1A
, hard masks
102
of silicon nitride are conventionally formed on a semiconductor substrate
101
. Hard masks
102
define a shallow trench
103
that is subsequently formed in substrate
101
. Shallow trench
103
is then filled with a dielectric
104
(FIG.
1
B), which is TEOS in this example. Portions of dielectric
104
above hard masks
102
are planarized by chemical-mechanical planarization (
FIG. 1C
) and, thereafter, hard masks
102
are stripped (i.e. removed) (
FIG. 1D
) using a conventional wet strip process.
Typically, there will be portions of dielectric
104
that are left extending above trench
103
upon removal of hard masks
102
. The height of this extended portion is referred to as step height and is depicted in
FIG. 1D
as step height
105
. The step height results in topography (i.e. uneven surface) that is propagated to overlying layers. In
FIG. 1E
, conductive lines
106
(e.g., bit lines made of polysilicon), oxide-nitride-oxide (“ONO”) layer
107
, conductive layer
108
(e.g., polysilicon), and metal layer
109
(e.g., tungsten silicide) follow the topography caused by the step height. As shown in
FIG. 1F
, a magnified view of area
120
shown in
FIG. 1E
, sections
121
-
123
of conductive lines
106
have varying thicknesses because of the step height. Section
121
can be thicker than sections
122
or
123
by as much as 2000 Å in some instances. Thickness variation is also present in other layers overlying dielectric
104
. If the thickness variation is large enough, the reliability and functionality of the device being fabricated will be adversely affected. For example, thickness variations can result in incomplete (or excessive) etching of conductive layer
108
and metal layer
109
during the formation of word lines, thereby causing shorts (also known as “stringers”) between word lines.
From the foregoing, a method for reducing the step height of STI structures is highly desirable.
SUMMARY OF THE INVENTION
The present invention relates to a method for reducing the step height of STI structures.
In accordance with the invention, a method for reducing the step height of a shallow trench isolation structure includes the acts of: (a) forming a trench in a semiconductor substrate; (b) filling the trench with a dielectric material; (c) planarizing the dielectric material a first time; (d) planarizing the dielectric material a second time; and (e) forming overlying layers on the dielectric material.
In one embodiment, a hard mask is formed on a semiconductor substrate to define a subsequently formed trench. The trench is filled with a dielectric material, which is then planarized. The hard mask is stripped and replaced with a resist mask. The dielectric material is then etched back, thereby reducing its step height. The resist mask is stripped and, thereafter, overlying layers are formed on the dielectric material. In another embodiment, the hard mask used to define the trench is used in the etch back of the dielectric material instead of a resist mask.
In another embodiment, a hard mask is formed on a semiconductor substrate to define a subsequently formed trench. The trench is filled with a dielectric material, which is then planarized by chemical-mechanical planarization. A portion of the hard mask is then stripped. The dielectric material is planarized again by chemical-mechanical planarization, thereby reducing its step height. The hard mask is completely stripped and, thereafter, overlying layers are formed on the dielectric material.
REFERENCES:
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patent: 5817567 (1998-10-01), Jang et al.
patent: 5854121 (1998-12-01), Gardner et al.
patent: 6060348 (2000-05-01), Yang et al.
patent: 6066543 (2000-05-01), Takahashi et al.
patent: 6238997 (2001-05-01), Chen et al.
patent: 6248667 (2001-06-01), Kim et al.
Peters, Laura, Senior ed., “Choices and Challenges for Shallow Trench Isolation”,Semiconductors International, Apr. 1999, pp. 68, 70, 72, 74, 76.
Fang Hao
Wang John Jianshi
Yang Wenge
Advanced Micro Devices , Inc.
Lytle Craig P.
Smith Matthew
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