Method for reducing the number of bits in a binary word represen

Coded data generation or conversion – Digital code to digital code converters – Tree structure

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341 51, 341106, 370 582, 39542107, 3954211, G06F 1200, H03M 730, H04Q 1104

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active

054816874

ABSTRACT:
A method for reducing the number of bits in a binary word (AI) which represent a series of addresses, called initial addresses, having a first step (E1) which successively extracts from each initial address (AI) at least one bit (C1) with a fixed rank; forms (1) an address called the selection address (AS) from each bit or bits (C1); extracts from each initial address (AI) a series of bits (C3, C6) using a format (M1i) selected from multiple predetermined first formats (M11, M12, M13, M14), as a function of the selection address; forms (2) with this series of bits (C3, C6) a binary word called the first relative address (AV1); and adds this first relative address to an address called the predetermined basic address (AB(M1i)) associated with the format (M1i) selected to determine this first relative address so as to obtain an address called the first reduced address (AT1) having a smaller number of bits than the initial address (AI); and wherein the basic address (AB(M1 i)) associated with the one (M1i) in the first formats, consists of successively considering the first formats; taking 0 for the basic address associated with the first format considered from the first formats; and taking for the value of each basic address associated respectively with the other first formats, the sum of the last basic address determined for the previously considered first formats, and the maximum relative address value which can be obtained using the last previously considered first format incremented by one unit.

REFERENCES:
patent: 4654654 (1987-03-01), Butler et al.
patent: 4933938 (1990-06-01), Sheehy
patent: 5128932 (1992-07-01), Li
patent: 5182799 (1993-01-01), Tamura et al.
patent: 5185860 (1993-02-01), Wu
patent: 5227778 (1993-07-01), Vacon et al.
patent: 5276868 (1994-01-01), Poole
patent: 5371499 (1994-12-01), Graybill et al.
patent: 5406278 (1995-04-01), Graybill et al.
IEE Proceedings Part E, vol. 135, No. 1, Janvier 1988, Stevenage, GB, pp. 55-59; P. Wolstenholme; `Filtering of Network Addresses in Real Time by Sequential Decoding`.
IEE Trans. on Communications, vol. 38, No. 7, Juillet 1990, New York, US, pp. 938-942; C. Kwok et al: `Cut-Through Bridging for CMAS?CD Local Area Networks`.
IEE INFOCOM 91; vol. 2, Avril 1991, Florida, US, pp. 515-524; Tong.sub.-- Bi Pei et al: `VLSI Implementation of Routing Tables: Tries and Cams`.
Philips Telecom and Data Systems Review, vol. 48, No. 2, Julin 1990, Hilversium, NL, pp. 15-22; W. Krick: `ATM--A Transfer Concept Not Only for Broadband Services`.

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