Metal treatment – Compositions – Heat treating
Patent
1975-09-22
1976-08-24
Rutledge, L. Dewayne
Metal treatment
Compositions
Heat treating
29578, 29580, 148175, 148187, 357 20, 357 34, 357 48, 357 88, 357 89, 357 91, H01L 21265, H01L 2120, H01L 2906
Patent
active
039765121
ABSTRACT:
The buried layer of an integrated circuit is produced by use of a grated mask. The growth of silicon dioxide in the exposed areas of the grate forms a stepped surface. Thereafter ion implantation in these areas and then merging the implanted regions forms a single buried region having a corrugated surface on which an epitaxial layer is grown. Such corrugated surface reduces the defect regions in the epitaxial layer.
REFERENCES:
patent: 3260902 (1966-07-01), Porter
patent: 3283223 (1966-11-01), DeWitt et al.
patent: 3436282 (1969-04-01), Shoda
patent: 3510736 (1970-05-01), Dingwall
patent: 3600241 (1971-08-01), Doo et al.
patent: 3717790 (1973-02-01), Dalton et al.
patent: 3902926 (1975-09-01), Perloff et al.
patent: 3916431 (1975-10-01), Khajezadeh
edel et al., "Stress Relief by Counterdoping" I.B.M. Tech. Discl. Bull., vol. 13, No. 3, Aug. 1970, p. 632.
Shepard et al., "Epitaxial Isolation and Device Fabrication" Ibid., vol. 13, No. 9, Feb. 1971, pp. 2548-2549.
Edel. W. A., "Stacking Fault Free Epitaxial Layers" Ibid., vol. 14, No. 5, Oct. 1971, p. 1654.
De Nora Vittorio
Polata Bohumil
Rutledge L. Dewayne
Saba W. G.
Signetics Corporation
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