Coating processes – Direct application of electrical – magnetic – wave – or... – Pretreatment of substrate or post-treatment of coated substrate
Patent
1996-11-26
1998-06-16
King, Roy V.
Coating processes
Direct application of electrical, magnetic, wave, or...
Pretreatment of substrate or post-treatment of coated substrate
427523, 427526, 438919, 438918, 438541, 438517, 148DIG40, B05D 306, H01L 21265
Patent
active
057666954
ABSTRACT:
The number of surface defects in semiconductor materials having a volatile species, particulary group-III nitride-based semiconductor devices, are reduced by first implanting species atoms into the semiconductor sample to fill some of the surface layer species vacancies created by growth and device fabrication processes, and then rapid thermal annealing the sample to repair broken bonds and crystalline defects and to move implanted species atoms from interstitial to substitutional sites. An optional third step deposits a dummy layer on the sample surface prior to implantation, making possible an implantation profile that places a higher density of species atoms in the surface layer than is attainable without the dummy layer and to inhibit species atoms from leaving the sample during high-temperature processing steps that follow.
REFERENCES:
patent: 4060427 (1977-11-01), Barile et al.
patent: 4818721 (1989-04-01), Wang
patent: 5403756 (1995-04-01), Yoshinouchi et al.
Pearton et al., "Process development for III-V nitrides", Materials Science and Engineering B38, 1996, pp. 138-146.
S.M. Sze, VSLI Technology, McGraw-Hill, 1988, pp. 127 and 355-362.
R.G. Wilson, "Implantation Range Statistics in III-V Materials", Journal of the Electgro-chemical Society, vol. 138, No. 3, Mar. 1991, pp. 718-722.
Nguyen Chanh N.
Wilson Robert G.
Denson-Low W. K.
Duraiswamy V. D.
Hughes Electronics Corporation
King Roy V.
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