Method for reducing soft error rates of memory cells

Semiconductor device manufacturing: process – Making passive device

Reexamination Certificate

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Details

C438S238000, C438S251000, C438S505000, C257SE21008, C257S561000, C257S632000, C257S646000, C257S661000

Reexamination Certificate

active

10936275

ABSTRACT:
In one embodiment, a method of fabricating a transistor for a memory cell includes the steps of performing a counter doping implant before or after a source/drain implant. The counter doping implant may comprise one or more implant steps that move a metallurgical junction formed by a well and a highly doped region closer to a surface of the substrate. The counter doping implant may also increase the concentration of the dopant of the well. The counter doping implant and the source/drain implant may be performed using the same mask. Transistors fabricated using embodiments of the present invention may be employed in memory cells to reduce soft error rates.

REFERENCES:
patent: 5013671 (1991-05-01), Havemann
patent: 5132235 (1992-07-01), Williams et al.
patent: 5330922 (1994-07-01), Erdeljac et al.
patent: 6117716 (2000-09-01), Manning
patent: 6660605 (2003-12-01), Liu
patent: 6670682 (2003-12-01), Mouli
RAM Reliability: Soft Errors, Apr. 14, 1998, pp. 1-3, [retrieved on Sep. 19, 2003], retrieved from the internet: URL:http://www.crystallineconcepts.com/ram/ram-soft.html/.

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