Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2002-05-08
2003-07-01
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S112000, C326S082000
Reexamination Certificate
active
06586974
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to signal output drivers of integrated circuits, and more particularly to a method for reducing short circuit current during power up and power down for high voltage pad drivers.
BACKGROUND OF THE INVENTION
Integrated circuits communicate with one another using digital signals. The digital state of zero (“0”, logic “low”) is represented by the range of voltages between a minimum voltage V
MIN
(e.g., 0 volts) of the potential voltage range of the signal and a voltage V
LOW
that is low relative to the total range of voltage. The digital state of one (“1”, logic “high”) is represented by the range of voltages between a voltage V
HIGH
that is high relative to the total range of voltages and a maximum voltage V
MAX
(e.g., 1.5 volts) of the potential voltage range of the signal.
To reduce power consumption and to scale down the size of CMOS logic, it is necessary to reduce the internal core power supply voltage. However, the input/output (I/O) pad drivers must typically use a higher-level power supply voltage in order to supply enough current to drive the loads connected to the pad and to meet certain industrial I/O standards such as the JEDEC 8[JEDEC I/O] series of standards. Accordingly, modern integrated circuits generally use a lower-level voltage power supply for the core or internal circuitry and a higher-level voltage power supply for the I/O circuitry. For example, a given integrated circuit may use a 1.5 V power supply for the core power supply and a 3.3±0.3 V power supply for the I/O power supply.
In order to provide a better understanding of the invention, a standard prior art output pad driver will first be discussed.
FIG. 1
depicts a schematic block diagram of a conventional output driver circuit
10
. As known in the art, the typical output driver circuit includes a pull-up leg
20
and a pull-down leg
30
. Each leg
20
,
30
typically includes a level shifter
26
,
36
having an input coupled to receive a respective core-level data signal PU
VDD
, PD
VDD
. The level shifter
26
,
36
steps up the voltage of the data signal from VDD to VDDH when the respective input data signal PU
VDD
, PD
VDD
is high. Each leg
20
,
30
also includes a pre-driver stage
22
,
32
(typically implemented with at least one complementary CMOS inverter) having an input coupled to receive a respective stepped-up data signal PU
VDDH
, PD
VDDH
. The pre-driver stage
22
,
32
produces pull-up and pull-down pre-drive signals PU_DRV, PD_DRV used to respectively control a pair of output driver pull-up and pull-down devices
24
,
34
. When enabled by its respective pre-drive signal PU_DRV, PD_DRV, one of the pull-up or pull-down devices
24
,
34
drives the output pad
6
to a respective high or low logic level.
Typically, the output driver pullup and pulldown devices
24
,
34
are complementary FET devices. In particular, the output driver pullup device
24
is a PFET having a source electrically coupled to the I/O power supply and a drain connected to the output pad. The gate of the PFET
24
is driven by the pullup pre-drive signal PU_DRV. Accordingly, when PU_DRV is driven low, PFET
24
turns on and drives the output pad to VDDH. Similarly, the output driver pulldown device
34
is an NFET having a source electrically coupled to the chip ground and a drain connected to the output pad. The gate of the NFET
34
is driven by the pulldown pre-drive signal PD_DRV. Accordingly, when PD_DRV is driven high, NFET
34
turns on and drives the output pad
6
to ground.
FIG. 2
is a schematic diagram of a conventional level shifter
100
. In the illustrative embodiment, the level shifter
100
receives a single-ended core-voltage-level signal IN on an input node
101
. Level shifter
100
converts the single-ended input signal IN to a differential input signal IN_N, IN_NN on nodes
102
,
103
. As known in the art, a differential signal comprises a pair of complementary signals. Level shifter
100
steps up the voltage level of the differential input signal IN_N, IN_NN to produce a differential output signal (OUT, OUT_N) on respective output nodes
104
,
105
.
In the illustrative embodiment, the level shifter
100
comprises two inverters
110
,
115
connected in series to produce the differential input signal pair IN_N, IN_NN. In particular, a first inverter
110
receives at a first input node
101
the single-ended input signal IN, and produces on node
102
the first half IN_N of the differential input signal pair IN_N, IN_NN. The second inverter
115
inverts the signal IN_N received on node
102
and produces on node
103
the complementary half IN_NN of the differential input signal pair IN_N, IN_NN. In the preferred embodiment, inverters
110
and
115
are complementary CMOS inverters each comprising a PFET
111
,
116
and an NFET
112
,
117
. The PFETs
111
,
116
and NFETs
112
,
117
are both gate-connected to the respective inverter input node
101
,
102
and drain-connected to the respective inverter output node
102
,
103
. The source of the PFET
111
,
116
of each inverter
110
,
115
is connected to the core-voltage-level power supply VDD and source of the NFET of each inverter
110
,
115
is connected to ground. The operation of complementary CMOS inverters is well-known in the art.
Differential input signal IN_N, IN_NN is fed into a level shifter
120
. Level shifter
120
is constructed with a pair of input NFETs
121
,
122
, each having a source connected to ground and drain connected to a complementary output node
104
,
105
. The gate of respective input NFETs
121
,
122
is connected to respective differential input node
102
,
103
; hence the respective amplifier input NFET
121
,
122
is controlled by respective differential input signals IN_N, IN_NN.
Level shifter
120
also includes a pair of output PFETs
123
,
124
, each having a source connected to the high-voltage-level power supply VDDH and a drain connected to a respective differential output node
104
,
105
. The gate of respective output PFETs
123
,
124
is connected to the complementary respective output nodes
105
,
104
of the level shifter
120
. The output PFETs
123
,
124
are relatively weak compared to the input NFETs
121
,
122
to allow the output signals OUT, OUT_N to be easily overdriven by the NFETS
121
,
122
.
During normal operation, when the input signal IN is a “1
VDD
”, differential input signals IN_N, IN_NN are “0
VDD
” and “1
VDD
” respectively. When signal IN_N is “0
VDD
”, input NFET
121
is off. Meanwhile, since signal IN_NN is “1
VDD
”, input NFET
122
is on, pulling complementary output node
105
to ground. Accordingly, complementary differential output signal OUT_N is “0
VDDH
”. When complementary output signal OUT_N is “0
VDDH
”, output PFET
123
turns on to pull output node
104
to VDDH. Hence, differential output signal OUT is “1
VDDH
”. Accordingly, the level shifter operates to convert a “1
VDD
” (i.e., high voltage level of VDD) seen at the input
101
of the level shifter to a “1
VDDH
” (i.e., high voltage level of VDDH) on the output node
104
of the level shifter
10
.
When the input signal IN is a “0
VDD
”, differential input signals IN_N, IN_NN are “1
VDD
” and “0
VDD
” respectively. When signal IN_NN is “0
VDD
”, input NFET
122
is off. Meanwhile, since signal IN_N is “1
VDD
”, input NFET
121
is on, pulling output node
104
to ground. Accordingly, output signal OUT is “0
VDDH
”. When complementary output signal OUT_N is “0
VDDH
”, output PFET
124
turns on to pull output node
105
to VDDH. Hence, complementary differential output signal OUT_N is “1
VDDH
”. Accordingly, when the input signal IN is a “0
VDD
”, the level shifter
100
outputs a “0
VDDH
” on the output node
104
of the level shifter
100
. (Of course, since a logical “0” is defined as ground in both the core- and I/O-level power supplies, “0
VDDH
” equals “0
VDD
”).
During power up or power down of the integrated circuit, there is a possibility that the core-level power supply VDD m
Humphrey Guy Harlan
Krzyzkowski Richard A
Agilent Technologie,s Inc.
Lam Tuan T.
Nguyen Hiep
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