Method for reducing selectivity loss in selective tungsten depos

Details Method for reducing selectivity loss in selective tungsten depos Method for reducing selectivity loss in selective tungsten depos

1991-11-12

1993-04-06

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437190, 437228, H01L 2144

Patent

active

052003604

ABSTRACT:
A method of forming a plug for electrical connection between two metallic layers on an integrated circuit substrate includes retaining an antinucleation resist layer atop an insulator layer through which the plug is to be formed. After a contact hole is etched through the insulator layer, the antinucleation resist layer is baked. Cleaning of an area exposed by said contact hole in order to minimize contact resistance occurs during a two step process of argon sputter etching and oxygen plasma descumming the exposed area. Because the argon sputter etch and the oxygen plasma descum uncover an annular region about the contact hole, a concentration of phosphorous within the insulator layer and a low temperature selective deposition are used to reduce the occurrence of unwanted nucleation. After selective deposition, the antinucleation resist layer is stripped and an upper metallic layer is formed.

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S. Wolf, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, Calif., 1990.

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