Method for reducing reactive ion etching (RIE) lag in...

Details Method for reducing reactive ion etching (RIE) lag in... Method for reducing reactive ion etching (RIE) lag in...

2005-05-31

2005-05-31

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S700000, C438S713000, C216S041000, C216S067000

Reexamination Certificate

active

06900136

ABSTRACT:
A method for reducing RIE lag (reaction ion etching lag) in a deep silicon etching process forming trench openings is described. The method can be carried out by either a photolithographic means wherein trench openings of the same planar area are patterned on the silicon substrate, or by a pressure means in which the chamber pressure during the reactive ion etching process is increased to reduce or eliminate the RIE lag effect. By increasing the chamber pressure at least 50% from that normally incurred in a reactive ion etching process, and preferably at least 100%, the RIE lag effect can be completely eliminated resulting in an inversed RIE lag in which a larger etch depth is achieved for the trench openings that have the smallest width.

REFERENCES:
patent: 5473186 (1995-12-01), Morita
patent: 6372655 (2002-04-01), Khan et al.

Affiliated with

Also associated with

Rating

Method for reducing reactive ion etching (RIE) lag in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for reducing reactive ion etching (RIE) lag in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing reactive ion etching (RIE) lag in... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3405572