Method for reducing program disturb during self-boosting in a NA

Details Method for reducing program disturb during self-boosting in a NA Method for reducing program disturb during self-boosting in a NA

1998-09-24

1999-11-23

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

36518517, G11C 1134

Patent

active

059912022

ABSTRACT:
A NAND flash memory system is programmed with minimal program disturb and pass disturb during self-boosting without resorting to impurity implantation for bit line isolation, to p-well biasing or to bit line biasing techniques. A program voltage is applied to a selected word line in the form of a plurality of short pulses while synchronously applying a pulsed pass voltage to the unselected word lines until the selected cell is programmed. The duration of the pulses and the time between pulses are chosen to minimize the program disturb of unselected cells, especially unselected cells on the selected word line, without causing pass disturb of any cell in the array.

REFERENCES:
patent: 5636162 (1997-06-01), Coffman
patent: 5815438 (1998-09-01), Haddad

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