Method for reducing power consumption of switching nodes in a ci

Details Method for reducing power consumption of switching nodes in a ci Method for reducing power consumption of switching nodes in a ci

1995-04-24

1997-10-28

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, 364491, 364488, G06F 1750

Patent

active

056825196

ABSTRACT:
A method for generating a low-power circuit from a Shannon graph having a plurality of primary inputs, a plurality of nodes including parent and child nodes, a first end-terminal, and a second end-terminal, each of the plurality of nodes having output edges associated therewith, includes the steps of: substituting the plurality of nodes and associated output edges with a plurality of cells, one cell for each node and output edge associated therewith, each cell including a plurality of elements; coupling a cell substituted for a parent node to cells substituted for child nodes of the parent node; and bypassing particular elements of child nodes having only one parent node.

REFERENCES:
patent: 4811237 (1989-03-01), Putatunda et al.
patent: 4960724 (1990-10-01), Watanabe et al.
patent: 5243538 (1993-09-01), Okuzawa et al.
patent: 5392221 (1995-02-01), Donath et al.
patent: 5487017 (1996-01-01), Prasad et al.
A. P. Chandrakasan et al., "Hyper-LP: A System For Power-Minimization Using Architectural Transformations," 1992, Proceedings of the International Conference on Computer Design, pp. 300-303.
A. Shen et al., "On Average Power Dissipation and Random Pattern Testability of CMOS Combinational Logic Circuits," 1992, Proceedings of the International Conference on Computer Design, pp. 402-407.
R. Murgai et al., "Decomposition for Minimum Transition Activity," 1994, Proceedings of the Low-Power Workshop, pp. 1-10.
V. Tiwari et al., "Technology Mapping for Low Power," 1993, Proceedings of the 30th ACM/IEEE Design Automation Conference, pp. 74-79.
C. Y. Tsui et al., "Technology Decomposition and Mapping Targeting Low Power Dissipation," 1993, Proceedings of 30th ACM/IEEE Design Automation Conference, pp. 68-73.
L. Benini and G. De Micheli, "State Assignment for Low Power Dissipation," 1994, Proceedings of EDAC'94, pp. 136-139.
M. Alidina et al., "Precomputation-Based Sequential Logic Optimization for Low Power," 1994, Proceedings of the International Conference on Computer-Aided Design, pp. 74-81.
R. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," 1996, IEEE Transactions on Computers, vol. C-35, No. 8, pp. 677-691.
D. A. Huffman, "A Method for the Construction of Minimum Redundancy Codes," 1952, Proceedings of the IRE, vol. 40 pp. 1098-1101.
A. V. Aho et al., "Algorithims on Graphs", 1974, The Design and Analysis of Computer Algorithms, Chapter 5, pp. 171-223.
G. D. Hachtel et al., "Re-Encoding Sequential Circuits to Reduce Power Dissipation," 1994, Proceedings of the International Conference on Computer-Aided Design, pp. 70-73.

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