Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
1998-04-10
2002-03-12
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S097000, C345S098000, C345S100000
Reexamination Certificate
active
06356260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to a method and an apparatus for conveying video data; and in particular, the present invention relates to a method and an apparatus for conveying video data which reduce power consumption and electromagnetic interference.
2. Background of the Invention
In a liquid crystal flat panel display, digital video data supplied by a host computer are converted into analog voltages which drive a display to produce the desired greyscale or color images.
FIG. 1
illustrates a block diagram of an exemplary flat panel display system.
In
FIG. 1
, a flat panel display system
10
includes a liquid crystal display (LCD) panel
100
which is, for example, a 640 pixels wide by 480 lines high VGA color TFT panel. In this illustration, LCD panel
100
has 640 columns and 480 lines (or rows) of pixels. Images are displayed on LCD panel
100
by activating each row of pixels sequentially while applying the appropriate voltages to the pixels of each column. The columns of LCD panel
100
are driven by display drivers, also known as column drivers. In a flat panel display system where the LCD panel includes only a small number of columns, a single display driver may be used to drive all the columns of the LCD panel. However, in display system
10
of
FIG. 1
, a bank of display drivers
120
A to
120
E are needed to support LCD panel
100
, each display driver driving a portion of a line of pixels on LCD panel
100
. In this example, display system
10
uses a single-bank configuration where display drivers
120
A to
120
E are serially arranged on one side of LCD panel
100
. Typically, display drivers
120
A to
120
E are mounted directly on the glass of LCD panel
100
. In this illustration, each of the display drivers
120
A to
120
E is capable of providing 240 analog output voltages to LCD panel
100
, representing 80 channels for each of Red, Green and Blue (RGB) subpixel output signals. Display drivers
120
A to
120
E drive different voltage levels onto LCD panel
100
to vary the brightness of each pixel. The rows of LCD panel
100
are driven by gate drivers
150
A to
150
E. Gate drivers
150
A to
150
E are activated sequentially to turn on one row of pixels at a time, allowing analog voltages driven onto the columns to be applied to each row of pixels in series.
Display drivers
120
A to
120
E receive video data, also called pixel data, from a timing controller
130
on data bus
140
. Typically, timing controller
130
is not mounted on the glass of LCD panel
100
. Timing controller
130
receives digital display data, or video data, from a host computer (not shown) on data lines
110
. Timing controller
130
“picks” the display data out one pixel at a time and synchronizes the pixel data with a video clock signal provided on line
112
. The pixel data, along with the clock signal are then delivered to display drivers
120
A to
120
E on data bus
140
. Specifically, timing controller
130
delivers the pixel data on data lines
142
and the clock signal on clock line
144
.
FIG. 2
is a block diagram of a display driver
200
, representative of any of display drivers
120
A to
120
E in FIG.
1
. In
FIG. 2
, display driver
200
is only one of a bank of display drivers, each operating in the same manner to provide one portion of a line of pixel data to LCD panel
100
. Referring to
FIG. 2
, during operation, timing controller
130
delivers pixel data to display driver
200
on data lines
220
and a clock signal on clock line
222
. Shift register
202
, which performs a control function, loads the input pixel data one pixel at a time from data register
204
into the respective latches in data latches
206
. In this illustration, data latches
206
comprises 240×6 latches for storing 240 pixels of 6-bit RGB data.
Timing controller
130
loads pixel data into display driver
200
until all 240 latches in data latches
206
are filled. In a display system comprising multiple display drivers, such as display system
10
in
FIG. 1
, timing controller
130
loads pixel data into display drivers
120
A to
120
E until an entire row of pixel data has been loaded. Then, display driver
200
loads the pixel data stored in data latches
206
into digital-to-analog converter (DAC) latches
208
. Thus in reference to display system
10
in
FIG. 1
, after an entire row of pixel data has been loaded into data latches of each of display drivers
120
A to
120
E, display drivers
120
A to
120
E then simultaneously load the row of pixel data into their respective DAC latches.
DAC latches
208
converts the digital signals to analog voltages which are then provided to a DAC output circuit
212
. DAC output circuit
212
drives the analog voltages onto the respective columns of LCD panel
100
.
While a new row of data is being loaded pixel by pixel into data latches
206
, the previous row of pixel data in DAC latches
208
is not overwritten until a full row of new pixel data has been loaded into data latches
206
.
In a high resolution flat panel display, such as flat panel display system
10
, the data bus, such as data bus
140
in
FIG. 1
, dissipates a significant amount of power and also generates a large amount of electromagnetic interference (EMI). Power dissipation is high because most existing displays use TTL voltage levels (3.3 volts CMOS levels) to transmit pixel data. In addition, high data rates and sharp transition edges generate significant EMI.
Efforts have been made to reduce the power dissipation and EMI generation in a flat panel display system. One commonly employed approach involves splitting the pixel data into two buses, each operating at half the data rate.
FIGS. 3
a
and
3
b
illustrate respectively the data bus configuration of a conventional display system and of another prior art display system employing a dual bus configuration for reducing EMI. Referring to
FIG. 3
a
, flat panel display system
300
a
has an 18-bit wide pixel data, comprising 1 bits for each of Red, Green, and Blue subpixel data. The pixel data is transmitted together with a 1-bit wide pixel clock. Thus, in a conventional flat panel display system such as display system
300
a
, 19 wires are required to transmit the pixel data and the pixel clock signal. In
FIG. 3
a
, timing controller
330
a
transmits the 18-bit pixel data on data bus
304
a
and the 1-bit pixel clock on clock line
302
a
to display drivers
320
aa
to
320
ae.
Referring to
FIG. 3
b
, display system
300
b
uses a dual bus configuration to transmit video data. Timing controller
330
b
splits up the 18-bit pixel data and transmits pixel data alternately over two 18-bit wide data buses
304
b
and
305
b
. Data buses
304
b
and
305
b
are connected alternately to display drivers
320
ba
to
320
bf
. Display system
300
b
has several disadvantages. First, although slower transition edges are obtained which can be effective in reducing EMI, the introduction of an additional data bus (data bus
305
b
) actually increases power dissipation and reduces noise immunity. Another disadvantage of display system
300
b
is that the number of data wires for transmitting pixel data is substantially increased. Specifically, the second data bus
305
b
adds 18 data wires to display system
300
b
. Thus; a total of 37 wires are now required to transmit the pixel data and the pixel clock, as opposed to the 19 wires required in the conventional display system in
FIG. 3
a
. The additional data wires consume valuable space on the PC board of the flat panel display. As flat panel displays become thinner, PC board space becomes a premium and introducing large number of additional data lines becomes unfeasible.
Therefore, it is desirable to reduce power dissipation and EMI generation in a flat panel display system without significantly increasing the number of data wires and without compromising noise immunity.
SUMMARY OF THE INVENTION
According to the present invention, reduced swing differential signals are used in combination with a multiple
Cook Carmen C.
Kovalick Vincent E.
National Semiconductor Corporation
Shalwala Bipin
Skjerven Morrill & MacPherson LLP
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