Method for reducing peak to peak jitter in a dual-loop delay...

Details Method for reducing peak to peak jitter in a dual-loop delay... Method for reducing peak to peak jitter in a dual-loop delay...

2001-08-14

2002-12-31

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Unwanted signal suppression

Reexamination Certificate

active

06501328

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates generally to micro-circuitry design. Specifically, this invention relates to a method for reducing peak to peak jitter in a dual-loop delay locked loop.
2. Background Art
In electronic circuits, the system power supply can be shown as an equivalent circuit
10
as shown in FIG.
1
. Specifically, the equivalent circuit
10
includes: a system power supply source
12
; a system resistance (Rs)
14
; a system inductance (Ls)
16
; and a system capacitance (Rc)
18
. Each of these system components
12
,
14
,
16
, and
18
represent an equivalent value of all of the combined respective components in the power supply system. The performance of the circuit
10
is frequency dependent. As shown in the graph of
FIG. 2
, as the frequency of the system increases, the resistance of the circuit increases as well. This increase in resistance continues until a peak
20
is reached at a resonance frequency. Finally, the resistance will subside at even higher frequencies.
The rate of increase in the resistance of the circuit as the frequency approaches its resonance value is quantified as a “Q” value. The “Q” value is calculated as Q=({square root over ( )}(L/C))/R; where L is the system inductance value; where C is the system capacitance value; and where R is the system resistance value. As shown in
FIG. 2
, under normal operations, the equivalent circuit
10
has a very high Q value
24
near the resonance frequency. A high current transient with the high Q region of the frequency band causes significant noise in the power supply system. Supply noise can result in such problems as signal jitter, signal stability, component or logic malfunction, signal interference, temperature variation, etc. Signal jitter is a significant problem in data signals because it results in uncertainty of the edge transition of the signal. This leads to loss of bandwidth and a subsequent loss of system performance.
It would be advantageous to decrease the Q value of the power supply system and thereby reduce supply noise. A reduced Q value
26
is also shown in FIG.
2
. This Q value
26
would have the advantage of substantially reducing the supply noise of the respective system.
FIG. 3
shows a prior art method of reducing the Q value for a delay locked loop (“DLL”) power supply system. A delay locked loop
32
is a component that may be included in an integrated circuit or “chip”. The delay locked loop
32
is a signal phase aligner. It shifts incoming clock signals 90 degrees out of phase with a corresponding data signal. This is necessary to ensure proper operation of the latches that receive both the data and clock signals. The delay locked loop
32
is just one of many types of components that are commonly included in an integrated circuit. Each of these components often has a dedicated power supply that is unique and separate from the power supplies of other components. The prior art method used in
FIG. 3
involves inserting a de-coupling capacitor
34
across the power supply in parallel with the delay locked loop
32
. However, the capacitor
34
takes up a significant amount of space on the chip. With chip space at a premium, a space efficient method of reducing power supply noise for a delay locked loop is needed.
SUMMARY OF INVENTION
In some aspects, the invention relates to a method for reducing power supply noise of a delay locked loop, comprising: supplying power to a delay locked loop; and connecting a resistance in parallel with the delay locked loop.
In another aspect, the invention relates to a method for reducing power supply noise of a delay locked loop, comprising: step of supplying power to a delay locked loop; and step of shunting a resistance in parallel with the delay locked loop.
In another aspect, the invention relates to an apparatus for reducing power supply noise of a delay locked loop, comprising: a delay locked loop; a power supply system connected to the delay locked loop; and a shunting resistor connected across the power supply system in parallel with the delay locked loop.
In another aspect, the invention relates to an apparatus for reducing power supply noise of a delay locked loop, comprising: means of supplying power to a delay locked loop; and means of connecting a resistance in parallel with the delay locked loop.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5926061 (1999-07-01), Usui
patent: 6417705 (2002-07-01), Tursi et al.

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