Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
1999-10-29
2004-12-14
Jones, Hugh (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S014000, C703S018000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06832180
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to noise problems in integrated circuits. More particularly, the present invention provides a method for inserting buffers into an integrated circuit layout during the place and route stage in order to reduce the overall noise introduced into conductive paths in a given design.
2. The Background Art
As the speed of signals within integrated circuits increases and the distance between conductive paths decreases, the problem of reducing the susceptibility of conductive paths to noise becomes increasingly important.
In the prior art conversion process between design and layout for integrated circuit systems, there are four major steps which are accomplished by system designers. Those four major steps include place and route of the standard cell design, physical design verification to ensure consistency between the layout and the schematic, parisitic extraction of the interconnect, and analysis of the extracted data to generate a noise analysis report.
When correcting the physical circuit layout in a prior art conversion process, a designer typically must either manually move wires and circuits in order to minimize or eliminate those noise problems, or may instead increase the size of the driver supplying signals to a conductive path which is deemed to be noise sensitive.
This manual process is extremely time-consuming and very tedious because moving conductive paths or increasing drivers is likely to cause new noise problems. Those new noise problems must then be corrected, potentially causing yet a third set of noise problems. Thus, manually correcting a circuit layout in order to solve noise problems often requires considerable effort and several very time-consuming iterations.
It would therefore be beneficial to provide a method for automatically determining potentially noisy areas within circuit layouts at the place and route stage, and for correcting problems related to areas of specific concern.
SUMMARY OF THE INVENTION
A method for minimizing noise in an integrated circuit is described, the method including choosing a net to be analyzed, determining that the total path length of conductive paths coupled to a driver within the net exceeds a maximum acceptable length for that driver according to the minimum acceptable noise levels for that given net, and inserting at least one buffer within the net at a position which is within the maximum acceptable length for conductive paths coupled to the driver.
REFERENCES:
patent: 5019724 (1991-05-01), McClure
patent: 5402356 (1995-03-01), Schaefer et al.
patent: 5596506 (1997-01-01), Petschauer et al.
patent: 5666288 (1997-09-01), Jones et al.
patent: 5799170 (1998-08-01), Drumm et al.
patent: 5838581 (1998-11-01), Kuroda
patent: 5859776 (1999-01-01), Sato et al.
patent: 6044209 (2000-03-01), Alpert et al.
patent: 6117182 (2000-09-01), Alpert et al.
patent: 6341365 (2002-01-01), Dwyer et al.
patent: 6405350 (2002-06-01), Tawada
Li et al.; “A repeater optimization methodology for deep sub-micron high performance processors”; IEEE Int. Conf. ICCD Proceedings; pp. 726-731; Oct. 1997.*
Yang et al.; Deep submicron on-chip crosstalk; IEEE Proc. 16th Inst. Meas. Tech. Conf.; pp. 1788-1793; May 1999.*
Davis et al.; Length, scaling, and material dependence of crosstalk between distributed RC Interconnects; IEEE Int. Conf. Interconnect Tech.; pp. 227-229; May 1999.*
Oh et al.; A scaling scheme and optimization methodology for deep sub-micron interconnect; IEEE Int. Conf. Computer Design; pp. 320-325; Oct. 1996.*
Lillis et al.: “Optimal wire sizing and buffer insertion for low power and a generalized delay model”; IEEE; pp. 437-447; Mar. 1996.*
Dhar et al.; “Optimun buffer circuits for driving long uniforn lines”; IEEE J. Solid State Ckts; pp. 32-40; Jan. 1991.*
Alpert et al.; “Buffer insertion for noise and delay optimization”; IEEE Proc. 98 Design Automation Conf.; pp. 362-367; Jun. 1998.*
Culetu et al.; “A practical repeater insertion method in high speed VLSI circuits”; IEEE 98 Design Automation Conf.; pp. 392-395; Jun. 1998.*
Cong; “Modeling and layout optimization of VLSI devices and interconnects in deep submicron design”; IEEE 97 Design Automation Conf.; pp. 121-126; Jan. 1997.*
Shah et al.; “Wiresizing with buffer placement and sizing for power-delay tradoffs”; IEEE 96 Proc. Design Automation Conf; pp. 346-351; Jan. 1996.
Smith Alan
Sutera Massimo
Jones Hugh
Martine & Penilla LLP
Sun Microsystems Inc.
LandOfFree
Method for reducing noise in integrated circuit layouts does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for reducing noise in integrated circuit layouts, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing noise in integrated circuit layouts will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3307639