Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-07-15
2002-11-12
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S691000, C438S753000, C438S759000
Reexamination Certificate
active
06479387
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of reducing micro-particle adsorption effects in a semiconductor process, and more particularly, to a method of reducing micro-particle adsorption effects during a chemical mechanical polishing (CMP) of a shallow trench isolation process.
2. Description of the Prior Art
Shallow trench isolation (STI) process is the mostly used device isolation technique in semiconductor processes with a line-width less than 0.35 um. This is because the STI fabrication process has both the advantages of excellent electric isolation effects and higher integration of semiconductor devices.
The prior method of fabricating STI first involves performing an reactive ion etching (RIE) process to form a shallow trench on a surface of a silicon substrate, followed by using a chemical vapor deposition (CVD), such as a high density plasma chemical vapor deposition (HDPCVD), to fill a silicon dioxide dielectric layer in the trench. A chemical mechanical polishing (CMP) process is then performed to have the surface of the semiconductor wafer form a plane surface. However, during the STI fabrication process related to the prior art, the process suffers a problem of unreliable control of micro-particles on the surface of the semiconductor wafer. That is because the interface of different materials on the surface of semiconductor wafer causes micro-particle adsorption during the CMP process.
Please refer to FIG.
1
and FIG.
2
. FIG.
1
and
FIG. 2
are schematic diagrams of performing a STI process on a surface of a semiconductor wafer
10
. As shown in
FIG. 1
, the semiconductor wafer
10
comprises a silicon substrate
12
, a silicon oxide layer
16
formed on the surface of the silicon substrate
12
, and a silicon nitride
18
formed on the surface of silicon oxide
16
. The prior method first involves using traditional photolithographic and etching processes to form a trench
14
on the surface of the silicon substrate
12
. A HDPCVD process is then performed to deposit a HDP oxide layer
20
on the surface of the semiconductor wafer
10
and fills the trench
14
with HDP oxide layer
20
.
As shown in
FIG. 2
, a CMP process is then performed. When performing the CMP process, the semiconductor wafer
10
is fixed horizontally and rotated on a polish pad of a CMP machine (not shown). A liquid supply system connected with the CMP machine sprays CMP polishing slurry on the surface of the rotating polish pad, so that the polishing slurry is evenly distributed on the surface of the polish pad and reacts with HDP oxide layer
20
on the surface of the semiconductor wafer
10
. At the same time, the semiconductor wafer
10
is pressed downward to contact the surface of the rotating polish pad so as to perform mechanical polishing on the HDP oxide layer
20
. As a result, the CMP process makes use of a chemical reaction provided by the slurry and a mechanical polishing provided by the-polish pad to rapidly remove the HDP oxide layer
20
by a predetermined thickness. Finally, the silicon nitride
18
underlying the HDP oxide layer
20
on the surface of the semiconductor wafer
10
is used as a stop layer. Operators can use refraction rate variation with time, a sudden change of polish pad temperature, or a friction difference to determine the endpoint of the CMP process.
The basic polishing slurry (pH=10) causes the Zeta potential on the surface of the silicon nitride layer
18
to be positive, but the Zeta potential on the HDP oxide layer
20
that fills the trench
14
is negative. Therefore, the micro-particle
22
with negative electrons of the polishing slurry is adsorbed to the surface of the silicon nitride
18
, and the surface of the HDP oxide layer
20
absorbs the micro-particle
24
with positive electrons
24
. Wherein the micro-particle
24
may be the silicon nitride particles with positive electrons that are abraded by the CMP process, and the micro-particles
22
,
24
which are adsorbed by static electricity on the surface of the semiconductor wafer
10
are not easily removed by a subsequent cleaning process.
Please refer to
FIG. 3
of the relationship between the zeta potential and the pH value. As shown in
FIG. 3
, in the environment of the pH=10, the surface potential of silicon nitride layer
18
is between 10 to 20 millivolt (mV) and the surface potential of HDP oxide layer
20
is between 5 to 20 mV. The result shows that the micro-particle adsorption effects during the CMP process is major caused by the different interface characteristics on the surface of the semiconductor wafer.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method of reducing micro-particles adsorption effects on the surface of the semiconductor wafer in a semiconductor process.
It is therefore another objective of the present invention to provide a method of reducing micro-particles adsorption effects on the surface of a semiconductor wafer in a CMP of STI process.
The present invention provides a method of reducing micro-particle adsorption effects during semiconductor processes, to thereby reduce micro-particle adsorption effects on a surface of a semiconductor wafer that comprises a silicon nitride layer. The method uses a polishing slurry containing surfactant to perform the CMP process, so that the surface of the silicon nitride layer and the micro-particles bare the same type of charges, so thereby reducing the micro-particle adsorption effects on the surface of the semiconductor wafer.
Using the surfactant in the polishing slurry changes the interface characteristics on the surface of semiconductor wafer; the present invention can efficiently reduce the micro-particle adsorption effects on the surface of the semiconductor wafer.
REFERENCES:
patent: 6042741 (2000-03-01), Hosali et al.
Ghyka Alexander
Hsu Winston
Macronix International Co. Ltd.
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