Method for reducing masking of errors when using a grid-based, "

Details Method for reducing masking of errors when using a grid-based, " Method for reducing masking of errors when using a grid-based, "

1989-08-25

1991-08-06

Atkinson, Charles E.

Excavating

371 226, G01R 3128

Patent

active

050383493

ABSTRACT:
Several methods for reducing the occurrence of masking of errors when using "Cross-Check" integrated circuit testing arrays and data compression devices such as multiple input shift registers are disclosed. The methods reduce the probability that successive faults within the logic circuit nodes of the integrated circuit will cancel one another by insuring that signals from logically proximate circuit nodes are either not provided sequentially to the data compression circuitry or are provided in such a way as to store any given error in at least two different locations.

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