Method for reducing junction capacitance and increasing current

Details Method for reducing junction capacitance and increasing current Method for reducing junction capacitance and increasing current

1995-06-07

1997-12-23

Tsai, Jey

Fishing, trapping, and vermin destroying

437 60, 437133, 437 28, 148DIG11, 148DIG51, 257200, H01L 21265

Patent

active

057007012

ABSTRACT:
This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.

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