Method for reducing DAC resolution in multi-bit sigma delta...

Details Method for reducing DAC resolution in multi-bit sigma delta... Method for reducing DAC resolution in multi-bit sigma delta...

2005-12-27

2005-12-27

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

Reexamination Certificate

active

06980144

ABSTRACT:
A method for reducing the resolution of a digital-to-analog converter in a multi-bit sigma-delta ADC is described. With the addition of digital sigma-delta modulators in the feedback path of a sigma-delta ADC, the truncation errors between the digital word output of the multi-bit sigma-delta ADC to the DAC input can be shaped to higher order than that of the quantization error. Thus, the DAC resolution can be reduced and the implementation of DEM for multi-bit DAC can be avoided. A preferred embodiment comprises selecting an outermost feedback loop in a sigma-delta ADC that has not been replaced and replacing it with a circuit with an equivalent transfer function. The circuit can be further enhanced with an additional term if the order of the noise shaping of the circuit is less than the order of the noise shaping of the sigma-delta ADC.

REFERENCES:
patent: 6313774 (2001-11-01), Zarubinsky et al.
patent: 6462687 (2002-10-01), Eshraghi et al.
patent: 6518903 (2003-02-01), Perraud et al.
patent: 6781533 (2004-08-01), Yap et al.
patent: 6825784 (2004-11-01), Zhang
patent: 6842129 (2005-01-01), Robinson
patent: 2002/0093442 (2002-07-01), Gupta

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