Method for reducing circuit area by grouping compatible storage

Details Method for reducing circuit area by grouping compatible storage Method for reducing circuit area by grouping compatible storage

1997-09-24

2000-01-25

Teska, Kevin J.

39550013, G06F 1750

Patent

active

060186224

ABSTRACT:
In a control block design methodology, a control block is designed, synthesized, and laid out. The control block includes one or more storage devices, such as flops. The flops include a header which buffers signals common to the flops and a storage cell for storing data. A flop grouping tool is used to merge flops having the same type of header into a flop having storage equivalent to the merged flops but using a single header. Multiple instances of the header may be deleted from the control block.

REFERENCES:
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patent: 5586319 (1996-12-01), Bell
patent: 5956257 (1999-09-01), Ginetti et al.
Kahng et al., "High-Performance Clock Routing Based on Recursive Geometric Matching," 28.sup.th ACM/IEEE Design Automation Conference, pp. 322-327. No Date.

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