Method for reducing charge loss in analog floating gate cell

Details Method for reducing charge loss in analog floating gate cell Method for reducing charge loss in analog floating gate cell

2007-11-20

2009-11-10

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185020, C365S185140, C365S185010, C365S185280

Reexamination Certificate

active

07616501

ABSTRACT:
A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly connected source/drain regions of a tunneling capacitor, which shares a floating gate with the first NVM transistor. During normal operation of the voltage reference circuit, the source/drain regions of the tunneling capacitor are connected to a second NVM transistor that has the same electrical and thermal characteristics as the floating gate of the first NVM transistor. As a result, charge loss from the floating gate of the first NVM transistor is advantageously minimized.

REFERENCES:
patent: 6137720 (2000-10-01), Lancaster
patent: 6898123 (2005-05-01), Owen
patent: 7280063 (2007-10-01), Ozalevli et al.
patent: 2002/0109539 (2002-08-01), Takeuchi et al.
patent: 2005/0219916 (2005-10-01), Georgescu et al.
patent: 2006/0067120 (2006-03-01), Drebinger

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