Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1998-09-09
2001-07-10
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S621000, C257S758000, C257S773000, C257S776000, C257S907000
Reexamination Certificate
active
06259162
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to conductive lines for semiconductor devices and particularly to metal lines for semiconductor memory devices.
BACKGROUND OF THE INVENTION
In semiconductor devices, conductive lines are used to interconnect between various devices or circuitry and or both. For example, power buses are typically made of a metal that is capable of carrying the required current necessary to operate the device.
In a semiconductor memory device, besides metal power buses, the memory array is interconnected by a grid of column (digit or bit) and row (word) lines. The word lines are typically made of polysilicon, topped with a metal silicide, while the bit lines comprise some form of metal.
The bit lines, in a memory array, run basically perpendicular to the word lines and in a parallel fashion to one another. A common characteristic between neighboring bit lines is the capacitive coupling that exists. Digit lines need to be at a specific precharge voltage in order to be read correctly during memory cell sensing. Since there is a capacitive coupling component between neighboring conductors, when a neighboring line is pulled high or low it can couple a digit line above or below the precharge voltage, thus affecting the device's ability to sense data correctly. As memory arrays become denser, the bit lines are crowded even closer together which in turn will increase the capacitive coupling.
It is desirable to reduce the capacitive coupling between conductive lines and in particular between neighboring bits lines of a memory array in order to provide a more efficient array. The present invention discloses a conductive line arrangement that may be used in any semiconductor device that uses substantially parallel conductors, such as in the memory array or a memory device, or the like, that indeed reduces capacitive coupling between neighboring lines (i.e., neighboring bits lines in a memory array).
SUMMARY OF THE INVENTION
A general embodiment of the present invention discloses a semiconductor device having conductive lines, where a first portion of the conductive lines are at a first level and a second portion of the conductive lines are at a second, vertically offset level to the first level, the second level extending in generally parallel relation to the first level.
A method to form the above structure comprises the steps of:
forming a first portion of the conductive lines at a first level; forming a second portion of the conductive lines at a second, vertically offset level to the first level; wherein the second level extends in generally parallel relation to the first level.
Another embodiment discloses a two level conductive structure fabricated in a semiconductor device, the structure comprising;
a suitable layer having trenches therein; a first level of conductive lines residing at least partially in the trenches; a second level of conductive lines, the second level of conductive lines having a major portion protruding above the surface of the layer and extending in generally parallel relation to the first level of conductive lines.
A method to form the two level conductive structure above comprises the steps of:
forming a plurality of trenches in a suitable layer; forming a conductive layer over the suitable layer, thereby at least partially filling the trenches; patterning the conductive layer to form a first and second level of conductive lines vertically offset from one another.
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Ma Kin F.
Stubbs Eric T.
Micro)n Technology, Inc.
Nadav Ori
Thomas Tom
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