Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2001-05-07
2003-03-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S197000, C438S235000
Reexamination Certificate
active
06534802
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More particularly, the present invention is in the field of fabrication of heterojunction bipolar transistors.
2. Related Art
In a silicon-germanium (“SiGe”) heterojunction bipolar transistor (“HBT”), a thin silicon-germanium layer is grown as the base of a bipolar transistor on a silicon wafer. The silicon-germanium HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Cutoff frequencies in excess of 100 GHz, which are comparable to the more expensive gallium-arsenide based devices, have been achieved for the silicon-germanium HBT.
The higher gain, speed and frequency response of the silicon-germanium HBT are possible due to certain advantages of silicon-germanium, such as a narrower band gap and reduced resistivity. These advantages make silicon-germanium devices more competitive than silicon-only devices in areas of technology where superior speed and frequency response are required.
But as with other transistors, excess base to collector capacitance can detrimentally impact the performance of a silicon-germanium HBT transistor, primarily by reducing its speed. The practical effect of a capacitor is that it stores electrical charges that are later discharged, and the extra time required to charge and discharge the excessive capacitance slows down the transistor. Because the benefits of high gain and high speed can be compromised by excess capacitance, it is a goal of silicon-germanium HBT design to reduce such excess capacitance to a minimum. By keeping the base to collector capacitance low, improved transistor performance is achieved.
Capacitance develops, for example, when two plates made of an electrically conducting material are separated by a dielectric such as silicon dioxide (“SiO
2
”). In general, capacitance is determined by the geometry of the device and is directly proportional to the area of the conductive plates and inversely proportional to the distance, or thickness, separating the two plates. Generally, capacitance is calculated using the equation:
Capacitance (C)=∈
0
k
A/t
(Equation 1)
where ∈
0
is the permitivity of free space, k is the dielectric constant of the dielectric separating the two plates, A is the size of the area where the plates overlap one another, and t is the thickness or separation between the two plates. From the Equation (1), it is seen that capacitance could be reduced by the presence of a dielectric with a lower dielectric constant k between the two plates. Alternatively, increasing the separation distance between the two plates, i.e. making the dielectric thicker, could also reduce the capacitance.
FIG. 1
shows an NPN silicon-germanium HBT structure
100
, which is used to describe the base to collector capacitance created by conventional silicon-germanium HBT fabrication processes. Certain details and features have been left out of
FIG. 1
which are apparent to a person of ordinary skill in the art. Structure
100
includes, among other components, intrinsic collector
134
, silicon-germanium base
122
, and emitter
120
. In exemplary structure
100
, intrinsic collector
134
is N type single crystal silicon which can be deposited epitaxially using a reduced pressure chemical vapor deposition (“RPCVD”) process. Silicon-germanium base
122
is P type silicon-germanium single crystal deposited epitaxially in a nonselective RPCVD process.
By way of background, because of the nonselective RPCVD process utilized to grow a silicon-germanium layer, the silicon-germanium base as well as other silicon-germanium regions are formed concurrently. The segments of the silicon-germanium layer formed over field oxide region
140
and field oxide region
142
are polycrystalline silicon-germanium and are referred to in this application as polycrystalline silicon-germanium segment
170
and polycrystalline silicon-germanium segment
172
. The segment of the silicon-germanium layer that is formed on top of intrinsic collector
134
and extrinsic collector regions
130
and
132
, and between field oxide regions
140
and
142
forms the base region of the SiGe HBT and is single-crystal silicon-germanium and is referred to as base
122
or single-crystal silicon-germanium base
122
in the present application.
Polycrystalline silicon-germanium segment
170
and polycrystalline silicon-germanium segment
172
do not function as part of the base of the silicon-germanium HBT but are electrically connected to the base. Situated above base
122
is emitter
120
, which forms a junction with base
122
and comprises N type polycrystalline silicon. Extrinsic collector region
130
and extrinsic collector region
132
are situated on each side of intrinsic collector
134
. Dielectric sections
126
provide electrical isolation to emitter
120
from base
122
. The interface between single-crystal silicon germanium base
122
and intrinsic collector
134
, and the interface between single-crystal silicon germanium base
122
and emitter
120
comprise the HBT's active area. Intrinsic collector
134
, single-crystal silicon germanium base
122
, and emitter
120
thus form the silicon-germanium HBT.
As further seen in
FIG. 1
, buried layer
114
, which is composed of N+ type material, is formed in semiconductor substrate
110
. Collector sinker
112
, also composed of N+ type material, is formed by diffusion of heavily concentrated dopants from the surface of collector sinker
112
down to buried layer
114
. Buried layer
114
and collector sinker
112
provide a low resistance electrical pathway from intrinsic collector
134
through buried layer
114
and collector sinker
112
to a collector contact (not shown). Deep trench structures
116
, field oxide region
140
, field oxide region
142
, and field oxide region
144
provide electrical isolation form other devices on semiconductor substrate
110
. Although structure
100
shows field oxide regions
140
,
142
, and
144
, for the purposes of processing a wafer, field oxide region
140
,
142
, and/or
144
could be composed of other types of isolation regions, for example shallow trench isolation regions, deep trench isolation, or local oxidation of silicon, generally referred to as “LOCOS”.
In a silicon-germanium HBT, base to collector capacitance, also referred to as base-collector capacitance in the present application, is between the base and collector regions and comprises intrinsic and extrinsic components. These components of the base-collector capacitance (“C
bc
”) are seen in FIG.
1
. Intrinsic C
bc
154
is between single-crystal silicon germanium base
122
and intrinsic collector
134
. Extrinsic C
bc
150
is between polycrystalline silicon-germanium segment
170
and extrinsic collector region
130
and through field oxide region
140
, while extrinsic C
bc
152
is between polycrystalline silicon-germanium segment
172
and extrinsic collector region
132
and through field oxide region
142
. Again, polycrystalline silicon-germanium segments
170
and
172
are physically and electrically connected to single-crystal silicon-germanium base
122
but do not function as part of the base. Polycrystalline silicon-germanium segments
170
and
172
overlap extrinsic collector regions
130
and
132
and lead to development of the extrinsic components of the total C
bc
. The total base to collector capacitance (“total C
bc
”) for the silicon-germanium HBT in structure
100
is the sum of intrinsic C
bc
154
, extrinsic C
bc
150
and extrinsic C
bc
152
.
Intrinsic C
bc
154
is the junction capacitance inherent in the silicon-germanium HBT device. The capacitance value of intrinsic C
bc
154
is determined by various fabrication parameters in the silicon-germanium HBT device and can only be reduced by altering the fabrication parameters and thus the performance of the device itself. As stated above, extrinsic C
bc
150
and C
bc
Farjami & Farjami LLP
Nelms David
Newport Fab LLC
Nguyen Thinh T.
LandOfFree
Method for reducing base to collector capacitance and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for reducing base to collector capacitance and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing base to collector capacitance and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3000624