Method for reducing analog PLL jitter in video application

Details Method for reducing analog PLL jitter in video application Method for reducing analog PLL jitter in video application

2005-08-05

2008-10-07

Hsia, Sherrie (Department: 2622)

Television

Synchronization

Automatic phase or frequency control

C348S540000, C348S547000

Reexamination Certificate

active

07432980

ABSTRACT:
The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.

REFERENCES:
patent: 6768385 (2004-07-01), Smith
patent: 7015973 (2006-03-01), Kim

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