Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2000-05-02
2002-07-23
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S107000, C438S110000
Reexamination Certificate
active
06423577
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for reducing an electrical noise inside a ball grid array package, and particularly to a method for embedding a plurality of capacitors between power pads and ground pads on a ball grid array package by a semiconductor package technology.
2. Description of Related Art
For the progress of semiconductor process technology, hundreds of thousands or even millions of transistors are built inside an integrated circuit chip, and therefore hundreds of I/O ports would be seen. If the hundreds of I/O ports are switching simultaneously, a bounce voltage on power supply and reference ground will be induced, so that computing results of the integrated circuit are unstable.
For resolving the problem of the unstable voltage and electrical noise, a prior method fixes a plurality of capacitors on a circuit board where the integrated circuit is located, to eliminate the electrical noise.
FIG. 1
is a top view of a prior plastic ball grid array (PBGA) package. The plastic ball grid array package
11
is fixed on a circuit board
13
, and a plurality of outside-connected capacitors
12
are provided around the PBGA package
11
. Each of the outside-connected capacitors is electrically connected to the power plane and ground plane (not shown) of the PBGA package
11
to eliminate an electrical noise induced on the power plane and ground plane.
The prior method requires a lot of capacitors of different sizes and different kinds on the circuit board
13
, and not only costs much but also occupies a large area on the circuit board. Moreover, the prior method is not suitable for use in the modern tendency to compactness.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to resolve the drawbacks of high cost and large area occupied as in the prior art. In order to accomplish the object, the present invention proposes a manufacturing method for reducing an electrical noise inside a ball grid array package. The manufacturing method fixes a plurality of inside-connected capacitors between power pads and ground pads of a substrate by semiconductor packaging technology. The plurality of inside-connected capacitors are directly, or through vias embedded conductive materials, electrically connected to a power plane and ground plane of the substrate to efficiently achieve the purposes of providing a stable voltage and filtering the electrical noise.
The manufacturing method of the present invention for reducing the electrical noise inside a ball grid array package can install the capacitors on is the top side of the substrate, or on the bottom side of the substrate or on both sides of the substrate. The most outstanding advantage of the present invention is to adhere the capacitors on the substrate in one time through a reflow soldering stove, therefore reducing the cycle time of process and raising throughput of the ball grid array package.
When the capacitors are installed on the top side of the substrate, the method of the present invention comprises the following steps: coating solder paste on a plurality of power pads and ground pads; coating adhesive glue beneath a plurality of capacitors; fixing the plurality of capacitors on the power pads and ground pads by said adhesive glue and solder paste; and solidifying the adhesive glue by passing the substrate through a reflow soldering stove.
When the capacitors are installed on the bottom side of the substrate, the method of the present invention comprises the following steps: coating solder paste on a plurality of power pads and ground pads; coating adhesive glue beneath the plurality of capacitors; fixing the plurality of capacitors on the power pads and ground pads by said adhesive glue and solder paste; placing a plurality of soldering balls; and solidifying the adhesive glue by passing the substrate through a reflow soldering stove.
When the capacitors are installed on both sides of the substrate, the present invention comprises the following steps: coating solder paste on a plurality of power pads and ground pads on said top and bottom sides of said substrate; coating adhesive glue beneath a plurality of capacitors; fixing the plurality of capacitors on the power pads and ground pads on said top and bottom sides of said substrate by said adhesive glue and solder paste; placing a plurality of soldering balls on the bottom side of the substrate; and solidifying the adhesive glue by passing the abstrate through a reflow soldering stove.
REFERENCES:
patent: 5605477 (1997-02-01), Wu et al.
patent: 5866942 (1999-02-01), Suzuki et al.
patent: 5949654 (1999-09-01), Fukuoka
patent: 6132543 (2000-10-01), Mohri et al.
patent: 6198136 (2001-03-01), Voldman et al.
patent: 6222260 (2001-04-01), Liang et al.
patent: 6261467 (2001-07-01), Giri et al.
Cheng Cheng-Chung
Shih Chia-Wen
Tsai Chen-Wen
Ladas & Parry
Picardat Kevin M.
Silicon Integrated Systems Corp.
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