Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-08-22
2003-04-15
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S752000, C257S753000
Reexamination Certificate
active
06548906
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to forming an interconnect structure and, more specifically, to a method for reducing a metal seam in an interconnect structure and a device manufactured by that method.
BACKGROUND OF THE INVENTION
Devices in the semiconductor industry continue to advance toward higher performance, while maintaining or even lowering the cost of manufacturing. Micro-miniaturization of semiconductor devices has resulted in higher performance, through increases in transistor speed and in the number of devices incorporated in a chip; however, this trend has also increased yield and reliability failures. As contact or via openings decrease in size, the aspect ratio, or the ratio of the depth of the opening to the diameter of the opening, also increases. With a higher aspect ratio, the use of aluminum-based metallization to fill the contact opening, results in electromigration and reliability failures. To alleviate reliability failures, the semiconductor industry has evolved to the use of tungsten, in certain device, for filling narrow, deep contact or via openings.
The switch to tungsten filled contact openings takes advantage of the improved conformal, or step, coverage that results from the use of a plasma enhanced chemical vapor deposition (PECVD) process. In addition, tungsten's high current carrying characteristics reduce the risk of electromigration failure. The conventional method of forming tungsten plugs in vias includes plasma etching of vias or contacts, photoresist striping and cleaning, adhesion layer and barrier metal deposition by physical vapor deposition (PVD) and tungsten deposition by PECVD. Typical adhesion and barrier materials used may consist of a stack of titanium and titanium nitride, respectively. The titanium reduces the contact resistance of the interconnect, and the titanium nitride is a protective layer against titanium attack by a tungsten hexaflouride gas that is used during tungsten deposition. In addition, tungsten adheres to titanium nitride very well, resulting in a mechanically stable tungsten plug. After tungsten plug filling, voids, or so-called tungsten seams, are often observed in the tungsten material. This is particularly the case, when the etched via profiles are straight. Such tungsten seams are commonly exposed during subsequent processing, such as during processes designed to remove unwanted tungsten from regions other then the contact opening. Moreover, in certain situations the size of the tungsten seam is increased due to exposure to the removal process. This often creates a difficult topology for subsequent metallization coverage as well as electrical device degradation, which is especially apparent as leakage in metal-oxide-metal MOM capacitor structures. Therefore, processes have been developed, either attempting to create seamless tungsten contact opening fills or repairing the seam or void in the tungsten fill. For example, one attempt involves altering the via etch profile so as to assume a tapered profile, thereby reducing the tungsten seam and allowing better tungsten fill. The tapered via profile helps reduce many of the tungsten seam issues, however, it often leads to increased contact resistance, which is also very undesirable.
Accordingly, what is needed in the art is an interconnect structure and method of manufacture therefor that does not experience the tungsten “seam” problems, as experienced in the prior art.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a method of manufacturing an interconnect structure. In an advantageous embodiment, the method includes forming a nucleation layer, including a first metal, over a barrier layer and within an opening formed in a dielectric layer. The method further includes forming an intermediate layer, including a second metal such as titanium nitride, over the nucleation layer and within the opening, and forming a plug portion layer, including the first metal, over the intermediate layer and within the opening. In one advantageous embodiment, the nucleation layer is tungsten and the intermediate layer is titanium nitride.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 5622894 (1997-04-01), Jang et al.
patent: 5700726 (1997-12-01), Huang et al.
patent: 5844318 (1998-12-01), Sandhu et al.
Wolf, Silicon Processing for the VLSI Era:vol. 2—Process Integration, 1990, pp. 132, 189-192.
Layadi Nace
Maury Alvaro
Talbott David L.
Zarneke David A.
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