Multiplex communications – Wide area network – Packet switching
Patent
1995-02-14
1996-07-23
Safourek, Benedict V.
Multiplex communications
Wide area network
Packet switching
370112, H04J 314
Patent
active
055397506
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a method for receiving a signal used in a synchronous digital telecommunication system.
The current digital transmission network is plesiochronous, that is each 2-Mbit/s basic multiplex system has a dedicated clock independent of any other system. It is therefore impossible to locate a single 2-Mbit/s signal in the bit stream of a higher-order system, but the higher level signal has to be demultiplexed through each intermediate level down to the 2 Mbit/s level to extract the 2-Mbit/s signal. For this reason, especially the construction of branch connections requiring several multiplexers and demultiplexers has been expensive. Another disadvantage of the plesiochronous transmission network is that equipment from two different manufacturers is not usually compatible.
The above drawbacks, among other things, have led to the introduction of the new synchronous digital hierarchy SDH specified in the CCITT recommendations G.707, G.708 and G.709. The synchronous digital hierarchy is based on STM-N transfer frames (Synchronous Transport Modules) located on several levels of hierarchy N (N=1,4,16 . . . ). Existing PCM systems, such as 2, 8- and 32-Mbit/s systems, are multiplexed into a synchronous 155.520-Mbit/s frame of the lowest level of the SDH (N=1). Consistently with the above, this frame is called the STM-1 frame. On the higher levels of hierarchy the bit rates are multiples of the bit rate of the lowest level. In principle, all nodes of the synchronous transmission network are synchronized into one clock. If some of the nodes should, however, lose connection with the common clock, it would lead to problems in the connections between the nodes. The phase of the frame must also be easy to recognize in the reception. For the reasons stated above, a pointer has been introduced in the SDH telecommunications, the pointer being a number which indicates the phase of the payload within the frame, i.e. the pointer indicates that byte in the STM frame from which the payload begins.
FIG. 1 illustrates the structure of an STM-N frame, and FIG. 2 illustrates a single STM-1 frame. The STM-N frame comprises a matrix with 9 rows and N.times.270 columns so that there is one byte at the junction point between each row and the column. Rows 1-3 and rows 5-9 of the N.times.9 first columns comprise a section overhead SOH, and row 4 comprises an AU pointer. The rest of the frame structure is formed of a section having the length of N.times.261 columns and containing the payload section of the STM-N frame.
FIG. 2 illustrates a single STM-1 frame which is 270 bytes in length, as described above. The payload section comprises one or more administration units AU. In the example shown in the figure, the payload section consists of the administration unit AU-4, into which a virtual container VC-4 is inserted. (Alternatively, the STM-1 transfer frame may contain three AU-3 units, each containing a corresponding virtual container VC-3). The VC-4, in turn, consists of a path overhead POH located at the beginning of each row and having the length of one byte (9 bytes altogether), and of the payload section in which there are lower-level frames also comprising bytes allowing interface justification to be performed in connection with mapping when the rate of the information signal to be mapped deviates from its nominal value to some extent. (Mapping of the information signal into the transmission frame STM-1 is described, e.g., in patent applications AU-B-34689/89 and FI-914746.
Each byte in the AU-4 unit has its own location number. The above-mentioned AU pointer contains the location of the first byte of the VC-4 container in the AU-4 unit. The pointers allow positive or negative pointer justifications to be performed at different points in the SDH network. If a virtual container having a certain clock frequency is applied to a network node operating at a clock frequency lower than the above-mentioned clock frequency of the virtual container, the data buffer will be filled up. This requi
REFERENCES:
patent: 4998242 (1991-03-01), Upp
patent: 5142529 (1992-08-01), Parruck et al.
patent: 5210762 (1993-05-01), Wieber et al.
CCITT Blue Book, Recommendation G.783, "Characteristics off Synchronous Digital Hierarchy(SCH) Multiplexing Equipment Functional Blocks", Aug. 1990, Annex B, Algorithm for pointer detection, pp. 53-55.
Annex PI to ETS DE/TM1015, ETSI, (European Telecommunications Standards Institute), Jan. 3, 1992, pp. 1-3.
CCITT Blue Book, Recommendation G.709, "Synchronous Multiplexing Structure", Geneva 1989, pp. 131-150.
Kivi-Mannila Arvi
Oksanen Toni
Patana Jari
Viitanen Esa
Nokia Telecommunications Oy
Patel Ajit
Safourek Benedict V.
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