Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
1998-06-29
2002-02-26
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S462000, C438S633000, C438S975000, C257S797000
Reexamination Certificate
active
06350658
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for realizing alignment marks on a semiconductor device during a manufacturing process including at least a Chemical Mechanical Polishing process step.
BACKGROUND OF THE INVENTION
As is well known, recent developments of the semiconductor devices manufacturing process have driven to a wider use of Chemical Mechanical Polishing (CMP) process steps to planarize dielectric or conductive layers.
The CMP technique is mainly used to planarize final or pre-metal oxide layers, but it's also used to planarize silicide oxide layers.
The CMP planarization step provides a drawback due to the fact that during such a process step alignment marks are planarized too. Therefore, the manufacturing process is carried on with some difficulties after the above CMP step.
Just as an example, let's now take in consideration some phase of the manufacturing process when contact vias are defined on an intermetal oxide.
As is well known, alignment marks are generally formed on the silicon wafer periphery. To provide metal contacts for the semiconductor device a pre-metal oxide must be planarized and this phase clears all the oxide which is present inside the region where alignment marks are formed.
For a better understanding of this problem let's consider the annexed
FIG. 1
which shows a semiconductor silicon wafer substrate portion
2
covered by a polysilicon layer
4
. Such a substrate portion presents some alignment marks
3
which are used by a stepper machine to align process masks during the further semiconductor device manufacturing process steps.
The polysilicon layer
4
is covered by a dielectric oxide layer
5
. According to a standard process, the oxide layer is etched and removed over the alignment marks region. Then, all the semiconductor portion shown in
FIG. 1
is covered by a first metal layer
6
. Such a metal layer
6
is conformal and follows very well the profile of the alignment marks, as clearly shown in FIG.
1
.
An intermetal oxide layer
7
is deposited over the first metal layer, as shown in FIG.
2
.
A CMP planarization step is then performed so that a smooth surface is obtained over the alignment marks region, as shown in FIG.
3
.
A subsequent etching step is performed to open contact vias. However, if the intermetal oxide layer has a high thickness, such oxide layer will not be removed by this further etching step.
FIG. 4
shows the result of the etching step on the intermetal oxide layer. The alignment marks portion is covered by a remaining planarized oxide layer.
This remaining oxide layer is transparent and an alignment step may still be performed, but a next second metal layer
8
deposition step cover definitively the alignment marks thereby losing the alignment option.
Some prior art solutions have been suggested to overcome this problem.
A first possible solution may be that of providing further process steps to open again the alignment marks region.
For instance, an opening may be defined over the alignment marks region covered by the intermetal oxide layer and the second metal layer. An etching step is performed to remove the second metal layer over the planarized intermetal oxide layer thereby allowing a stepper machine to “see” again the alignment marks through the transparent oxide layer.
This first solution is worked after the second metal layer deposition step.
A second solution is that of etching and removing a photoresist layer which is provided over the intermetal oxide layer before the CMP planarized step is performed.
Both the above solutions are expensive and require further process steps which are time consuming for the stepper machine.
SUMMARY OF THE INVENTION
One object of the present invention is that of providing a new alignment method to use after a CMP process step.
Another object of the present invention is that of providing a new technique for realizing alignment marks which may be traced by a stepper machine after a second metal deposition phase.
Another object of the present invention is that of providing alignment marks which could be detected even after a CMP process step.
A further object of the present invention is that of providing an electronic semiconductor device including alignment marks which remain visible for a stepper machine even after CMP and metal deposition process steps.
A solution idea behind this invention is that of increasing the thickness of the first dielectric oxide layer deposited around the alignment marks region so that a second dielectric layer would cover the marks region following the marks profile under the level of the first dielectric top surface.
An embodiment of the invention provides for a method as previously indicated and wherein the thickness of the first dielectric layer is high enough that the second dielectric layer covers said alignment marks portion under the level of the first dielectric top surface thereby preventing the CMP process step to planarize said portion.
One embodiment of the invention relates to a method including at least the following steps:
forming alignment marks on a portion of a semiconductor substrate;
masking said portion during a further deposition step of a first conductive layer covered by a first dielectric layer;
depositing a first conformal metal layer over said first dielectric layer and over said portion;
depositing a second dielectric layer over said first metal layer;
performing a CMP process step to planarize said second dielectric layer.
The features and advantages of the method and device according to the invention will be appreciated by the following description of a preferred embodiment given by way of non-limiting example with reference to the enclosed drawings.
REFERENCES:
patent: 5705320 (1998-01-01), Hsu et al.
patent: 5786260 (1998-07-01), Jang et al.
patent: 5801090 (1998-09-01), Wu et al.
patent: 5911108 (1999-06-01), Yen
patent: 5923996 (1999-07-01), Shih et al.
patent: 40 3138920 (1991-06-01), None
patent: 40 3161919 (1991-07-01), None
Betcher Susan D.
Jorgenson Lisa
Louie Wai-Sing
Seed Intellectual Property Law Group PLLC
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