Method for reading nonvolatile semiconductor memory...

Details Method for reading nonvolatile semiconductor memory... Method for reading nonvolatile semiconductor memory...

2001-03-13

2002-06-18

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240, C365S185270

Reexamination Certificate

active

06407945

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the field of semiconductors. The invention relates to a method for reading nonvolatile semiconductor memory configurations in which a high threshold voltage and a low threshold voltage are determined based on the charge state of a floating gate for a transistor.
In semiconductor memory configurations using, as memory cells, MOS transistors with a control gate and a floating gate, a leakage current problem arises. This problem can also be called the “moving bit problem”, or MB problem for short. In the MB problem, the floating gate loses its charge due to very small leakage currents over long times, which means there exists a limited data holding property. Because the leakage currents are exponentially dependent on the electrical field over the silicon dioxide insulation layer in which the floating gate is embedded, a marked reduction in the leakage currents can be expected if the electrical fields are successfully reduced to a large extent in the zero-current state of the semiconductor memory configuration. As a consequence, the threshold voltages V
T
in the high V
T
state and in the low V
T
state of the transistor should also be as low as possible. The threshold voltages are known to stipulate the memory state of the transistor by virtue of high V
T
and low V
T
logic states being assigned to “0” and “1”, or vice-versa.
Another general problem with nonvolatile semiconductor memory configurations is that identical memory cells can have different programming speeds due to variations in technology, for example, when they are manufactured. As a result, different threshold voltages may arise for the transistors in these memory cells.
When reading nonvolatile semiconductor memory configurations, the aforementioned logic states high V
T
or high threshold voltage and low V
T
or low threshold voltage of the transistor need to be distinguished for each of the individual cells. For reliable reading, the difference between the two threshold voltages high V
T
and low V
T
should be as large as possible. The difference cannot be increased arbitrarily, however, because the level of the high V
T
, i.e., the high threshold voltage, state is determined by the negative (for NMOS) or positive (for PMOS) quantity of charge that can be applied to the floating gate of the transistor, and hence is limited by the available voltages. The difference cannot be increased arbitrarily also because the low threshold voltage low V
T
must always be higher than 0 V (for NMOS) or lower than 0 V (for PMOS) due to the fact that the transistor would otherwise be normally on, even when not selected.
For the aforementioned leakage current problem, there is still no satisfactory solution at present. The only factor being considered is the use of a UV shift, i.e., raising the threshold voltage in the zero-charge state, that is to say, after discharge by UV irradiation, to reduce electrostatic fields over the oxide insulation layer.
Different programming speeds of the individual memory cells can be allowed for, per se, by intelligent programming, where each memory cell is allocated its required threshold voltage. However, such a procedure is extremely time consuming and requires greater effort for construction and in the peripheral area.
Negative (for NMOS) or positive (for PMOS) threshold voltages for low V
T
can be prevented by using the aforementioned intelligent programming to check the respective threshold voltage reached to prevent it from falling below (for NMOS) or rising above (for PMOS) the 0 V limit. Such intelligent programming places additional demands on the construction of the circuit. Finally, connecting a selection transistor upstream in addition to the transistor can also prevent a flow of current, even if the transistor, that is to say the actual memory cell, is over-programmed and becomes normally on. Such an additional selection transistor significantly increases the chip area required, however, and is, therefore, extremely cost intensive.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for reading nonvolatile semiconductor memory configurations that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that, while overcoming the leakage current problem, ensures a large difference between the threshold voltages, of which low V
T
can even assume negative (for NMOS) or positive (for PMOS) values.
The objectives of the invention are achieved by applying a reverse bias between the bulk and the source of the transistor.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for reading non-volatile semiconductor memory configurations including determining a high threshold and a low threshold voltage based on a charge state of a floating gate for a transistor, and applying a reverse bias between a bulk and a source of the transistor during reading.
In accordance with another mode of the invention, the low threshold voltage is allowed to assume negative voltage values for NMOS transistors and to assume positive voltage values for PMOS transistors.
In accordance with a further mode of the invention, applying the reverse bias expands the window between the high threshold voltage and the low threshold voltage.
In accordance with an added mode of the invention, the window between the high threshold voltage and the low threshold voltage is left constant by applying the reverse bias.
In accordance with an additional mode of the invention, by applying the bias, a threshold voltage for NMOS transistors is shifted by &ggr;({square root over (−V
SB
+2+L &phgr;
f
+L )}−{square root over (2&phgr;
f
+L )}) and a threshold voltage for PMOS transistors is shifted by −&ggr;({square root over (V
SB
−2+L &phgr;
f
+L )}−{square root over (−2&phgr;
f
+L )}) by applying the bias, where &ggr; is the substrate control factor and &phgr;
f
is the Fermi voltage of the bulk.
The inventive method for reading memory cells in a nonvolatile semiconductor memory configuration is based on the utilization of the substrate control effect, described as follows: when a reverse bias V
SB
is applied between the bulk and the source of an NMOS or PMOS transistor, the threshold voltage thereof is shifted by:
&ggr;({square root over (−V
SB
+2+L &phgr;
f
+L )}−{square root over (2+L &phgr;
f
+L )}),
where V
SB
<0 and &phgr;
f
>0 for NMOS, and
−&ggr;({square root over (V
SB
−2+L &phgr;
f
+L )}−{square root over (−2&phgr;
f
+L )}),
where V
SB
>0 and &phgr;
f
<0 for PMOS, &ggr;=substrate control factor, and &phgr;
f
=Fermi voltage of the bulk, that is to say, Fermi voltage of p-conductive or n-conductive silicon.
Thus, applying the reverse bias V
SB
between the bulk and the source allows an inherently normally-on memory cell having a negative (for NMOS) or positive (for PMOS) threshold voltage for a bulk voltage of 0 V to be off even with a positive (for NMOS) or negative (for PMOS) gate voltage.
In accordance with a concomitant mode of the invention, the drain and the source of the transistor are each placed at different potentials when the reverse bias has been applied.
The method according to the invention allows a series of significant advantages that cannot be readily achieved with the prior art.
First, if the distance between the high threshold voltage high V
T
and the low threshold voltage low V
T
, that is to say, the V
T
window, is left the same, then the high threshold voltage high V
T
can be lowered. Accordingly, if no external voltages are applied to the semiconductor memory configuration, a smaller electrical field exists over the silicon dioxide insulation layer in the high threshold voltage high V
T
state, which results in smaller leakage currents, in other words, in a lower leakage current susceptibility.
Second, lowering the relatively high threshold voltage high V
T
has the advant

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