Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-10-31
2003-10-28
Nguyen, Vanthu (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185270, C365S185330
Reexamination Certificate
active
06639836
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method for reading a flash memory cell. More particularly, the present invention relates to a method for reading a flash memory cell with silicon-oxide
itride/oxide-silicon (SONOS) structure.
2. Background of the Invention
The memory device is a semiconductor device used for storing information or data. When the functions of the microprocessor increase and a large amount of programs and operations are required to be executed by the software, the demand for the memory increases. For fabricating high-capacity and inexpensive memory to satisfy this demand, fabricating the memory device has become a driving force challenging high integration technique and process.
Flash memory can perform programming, erasing and reading many times and can retain information even when power is interrupted, so it is widely used in personal computers and electrical apparatus.
The typical flash cell is an erasable programmable read-only memory with tunnel oxide (ETOX) cell. The ETOX cell is programmed by channel hot-electron (CHE) and is erased by Fowler-Nordheim (F-N) tunneling through the source side.
Moreover, the floating gate and the control gate of the ETOX cell are made of doped polysilicon. The electrons injected into the polysilicon floating gate are delocalized when the memory cell is programmed. However, if there are defects in the tunneling oxide under the polysilicon floating gate of the ETOX cell, current leakage of the device occurs easily and affects reliability of the device.
Therefore, in order to solve the problem of the gate induced drain leakage current of the ETOX memory cell, a flash memory cell with silicon-oxide
itride/oxide-silicon (SONOS) structure has been provided. The flash memory cell with SONOS structure comprises a charge trapping layer to replace the polysilicon floating gate. The charge trapping layer is made of silicon nitride between two oxide layers. When the memory cell is programmed by applying a bias to the control gate and source/drain regions, hot holes are generated at the channel adjacent to the source region and are injected into the charge trapping layer. Since the charge trapping layer is a dielectric layer, the hot holes injected into the charge trapping layer are not delocalized but are localized and have a Gauss distribution. For this reason, the sensitivity of the memory cell toward the defects in the tunneling oxide layer is smaller and the phenomenon of the gate induced drain leakage current is reduced.
However, with the flash memory cell with SONOS structure, since the electrons are localized in the charge trapping layer, current leakage easily occurs so as to make mistakes during the reading of the cell.
SUMMARY OF INVENTION
The present invention also provides a method for reading a flash memory cell with SONOS structure in order to improve the operation efficiency of the memory cell.
The present invention provides a method for reading a flash memory cell with SONOS structure. The flash memory cell with SONOS structure includes a P-well in a substrate, a tunneling oxide layer on the substrate, a charge trapping layer on the tunneling oxide layer, a dielectric layer on the charge trapping layer, a gate conductive layer on the dielectric layer, and source and drain regions in the substrate adjacent to the gate conductive layer. The flash memory cell with SONOS structure is read by applying a positive voltage to the drain region, floating the source region, grounding the P-well to generate gate induced drain leakage current and determining the gate induced drain leakage from the drain region to read the data in the memory cell.
According to the embodiment of the present invention, the flash memory cell with SONOS structure is read by applying 3 to 5V to the drain region, floating the source region, grounding the P-well to generate gate induced drain leakage current and determining the gate induced drain leakage from the drain region to read the data in the memory cell. If the charge trapping layer
104
adjacent to the drain region
114
is programmed, i.e., the charge trapping layer
104
has electrons, a large gate induced drain leakage current is detected because a large field is generated between the charge trapping layer
104
and the drain region
114
. If the charge trapping layer
104
adjacent to the drain region
114
is not programmed, i.e., the charge trapping layer
104
has no electrons or has holes, only a small gate induced drain leakage current is detected because the generated field between the charge trapping layer
104
and the drain region
114
is small. Therefore, the magnitude of gate induced drain leakage current represents the digital information “one” or “zero” stored in the flash cell. Furthermore, for increasing the gate induced drain leakage (GIDL) current, a negative voltage of about −3 to −5V is applied to the gate conductive layer
108
.
Since the tunneling oxide layer of the SONOS flash memory cell according to the present invention is thinner than that of the ETOX memory cell of the prior art, the electrons can more easily tunnel through the former than through the latter during the programming or erasing operation. Therefore, the present invention can improve the operation efficiency of the flash memory device.
The tunneling oxide layer is thinner, so that a low operation voltage can be used during the programming or erasing operation. Therefore, the dimension of the memory cell can be scaled down to achieve the objective of high integration.
Moreover, the magnitude of gate induced drain leakage current is related to the thickness of the tunneling oxide layer. The thinner the tunneling oxide layer, the larger the gate induced drain leakage current. For example, gate induced drain leakage current of a cell having a tunneling oxide layer with a thickness of 20 Angstroms is 1000 times than that of a cell having a tunneling oxide layer with a thickness of 90 Angstroms. Therefore, if the tunneling oxide layer is about 20 Angstroms and a bias about 3.5V is both applied to the drain region and the gate conductive layer, a micro Ampere order of gate induced drain leakage current can be detected to read the digital information stored in the flash cell.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5742541 (1998-04-01), Tanigami et al.
Hsu Hann-Jye
Huang Chiu-Tsung
Hung Chih-Wei
Jiang Chyun IP Offices
Nguyen Vanthu
Powerchip Semiconductor Corp.
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