Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2002-05-21
2003-11-25
Mai, Son (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S190000
Reexamination Certificate
active
06654271
ABSTRACT:
This application claims priority from German application no. 10124752.4, filed with the German Patent Office, Germany, on May 21, 2001, pursuant to 35 U.S.C. 119(a)-(d).
FIELD OF THE INVENTION
The invention features a method for reading out and storing binary memory cell signals and circuit arrangement. In particular, the present invention relates to binary memory cell arrays, and in particular relates to a method and a circuit arrangement for reading out binary memory cell signals from a memory cell array and for storing binary memory cell signals in a memory cell array, in which a signal transit time of the binary memory cell signals is minimized.
BACKGROUND OF THE INVENTION
In digital memories (RAM, DRAM, SRAM), an information item stored digitally in the form of binary memory cell signals has to be transferred to an output terminal of the circuit arrangement (chip). Memory cells are conventionally arranged in memory cell arrays having a size of 512×128 for example. In this case, 512 word lines can be activated in order to load a binary information item into the respective memory cell array. In the circuit arrangement specified above, 128 bit line pairs serve for reading out the corresponding binary information or for transferring the binary memory cell signals from the memory cell array and for storing binary memory cell signals in the memory cell array.
A bit line pair usually comprises two lines having complementary binary signal states. On account of the usually highly complex circuit arrangement, the bit line pairs cannot be used for forwarding binary memory cell signals directly to externally accessible output terminals. Besides a complex line structure, the binary memory cell signals additionally have to be regenerated or amplified in sense amplifiers or latches. In this case, it is necessary to arrange the sense amplifiers together with various switching transistor pairs in order that an information item present on bit line pairs is finally conducted away to an output terminal.
FIG. 1
shows a known circuit arrangement for reading out binary memory cell signals from memory cell arrays and for storing binary memory cell signals in memory cell arrays, individual memory cell arrays SZF and power supply lines being arranged in different planes.
Such memory cell arrays (for forming SRAMs, DRAMs) are described for example in WO 00/57422 A1 and DE 19917079.7, filed on Apr. 15, 1999.
Usually, a plurality of memory cell arrays are combined to form a unit. The binary memory cell signals are transferred to bit line pairs BL by the activation of word lines WL. The binary memory cell signals are transferred to sense amplifiers S/A, where the generally very low signal levels, which may be, for example, 100 mV or less, are brought to a defined logic level.
By means of a column control signal, the amplified binary memory cell signals are transferred by means of a local data line switching unit to a local data line pair formed from a local data line LDQ and a complementary local data line bLDQ. A central element of the conventional circuit arrangement shown in
FIG. 1
is provided in the form of a main data line switching unit MDQS. The binary intermediate signals provided on the local data lines are transferred, in a manner dependent on a row control signal fed via a row control line, to the main data line pair formed by a main data line MDQ and a complementary main data line bMDQ.
The main data line pair MDQ, bMDQ is designed in such a way that the amplified, transferred binary memory cell signals can be transferred to external terminal units (not shown).
One disadvantage of such conventional circuit arrangements for reading out binary memory cell signals from at least one memory cell array or for storing binary memory cell signals in at least one memory cell array is that large coupling capacitances occur between the main data line MDQ and the complementary main data line bMDQ and also between the main data lines and other adjacent data lines or power lines. Such coupling capacitances are caused, inter alia, by a small distance between the main data line MDQ and the complementary main data line bMDQ governed by the conventional circuit design.
Furthermore, in a disadvantageous manner, these two lines lie at a predetermined distance, which is predetermined inter alia by a required interference suppression, next to one another and run over the entire chip area without taking account of the location at which data are transferred from memory cell arrays to the main data line pair.
In a further disadvantageous manner, chip area serving no specific function is taken up. However, occupation of sections of the chip area with unrequired main data line pairs has the result that required main data line pairs have to be arranged at an excessively small distance, whereby a coupling capacitance between the main data line MDQ and the complementary main data line bMDQ is increased further.
Such an increase in coupling capacitances leads in a disadvantageous manner to an increase in signal transit times for binary memory cell signals which are to be transferred from at least one memory cell array via bit line pairs BL, a sense amplifier S/A, a local data line pair LDQ, bLDQ, a main data line switching unit MDQS and a main data line pair MDQ, bMDQ to a terminal unit (not shown) for an external terminal.
On account of fluctuations in the specifications during memory fabrication, caused by the technological fabrication processes, these increases in a signal transit time have a disadvantageous effect on a data access time.
SUMMARY OF THE INVENTION
Consequently, it is an object of the present invention to provide a method and a circuit arrangement for reading out binary memory cell signals from at least one memory cell array or for storing binary memory cell signals in at least one memory cell array in which a signal transit time of the binary memory cell signals is minimized.
The heart of the invention is a circuit arrangement in which coupling capacitances are reduced by enlarging a distance between a main data line and a corresponding complementary main data line or another adjacent line, or reducing a length of a main data line pair.
The invention's method for reading out binary memory cell signals from at least one memory cell array and for storing binary memory cell signals in at least one memory cell array, in which a signal transit time of the binary memory cell signals between at least one memory cell and at least one output terminal is reduced, has the following steps:
a) application of at least one binary memory cell signal to at least one bit line pair in a manner dependent on an activation of a word line;
b) switching-through of the binary memory cell signal from the bit line pair to a local data line pair via at least one sense amplifier, in order to obtain defined logic levels on the local data line pair;
c) switching-through of the amplified binary memory cell signal by means of at least one main data line switching unit from the local data line pair to at least one main data line pair, which is formed by at least one main data line and at least one complementary main data line, binary memory cell signals being transferred from memory cells arranged in a first memory cell region to at least one first main data line pair and binary memory cell signals being transferred from memory cells arranged in a second memory cell region to at least one second main data line pair; and
d) outputting of the amplified, transferred binary memory cell signals via the first main data line pair and the second main data line pair.
In accordance with one preferred development of the present invention, coupling capacitances between the second main data line and the second complementary main data line are reduced by enlargement of the distance between the second main data line and the second complementary main data line in the second memory cell region.
In accordance with a further preferred development of the present invention, coupling capacitances between the first main data line and the first
Chrysostomides Athanasia
Pfefferl Karl-Peter
Savignac Dominique
Fish & Richardson P.C.
Mai Son
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