Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2005-09-13
2005-09-13
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S212000
Reexamination Certificate
active
06944749
ABSTRACT:
A method for decoding instructions in an execution package with a processor includes using an assembler to assemble instructions into different execution packages. Each instruction has an identification segment and an instruction segment. The method also includes using the assembler to reorder the instructions by separating identification segments from instruction segments, grouping all identification segments of the execution package together, and grouping all instruction segments of the execution package together. The method uses the processor to decode identification segments of the instructions at the same time, and adds a length of each identification segment together to calculate a total length of the execution package.
REFERENCES:
patent: 5948096 (1999-09-01), Ginosar et al.
patent: 6260134 (2001-07-01), Zuraski et al.
patent: 6418527 (2002-07-01), Rozenshein et al.
Faraday Technology Corp.
Hsu Winston
Treat William M.
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