Method for providing minimal size test vector sets

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364580, G01R 313183

Patent

active

054447178

ABSTRACT:
A method of testing an integrated circuit having a plurality of pins includes the steps of providing a functional test set having an ordered group of test strings wherein each element of the test string is related to one of the pins of said integrated circuit. The group of test strings is searched to locate a sequence of test strings having a undesirable pattern. The undesirable pattern can be a pattern in which none of the elements associated with the test string changes or a pattern in which a reference element and at least one other element of the test string changes. When a sequence of test strings having the undesirable pattern is located, the group of test strings is processed to correct the undesirable pattern. When all the vector sequences having an undesirable patterns are corrected, the group of test vectors is applied to the input pins of the integrated circuit.

REFERENCES:
patent: 4500993 (1985-02-01), Jacobson
patent: 4862399 (1989-08-01), Freeman
patent: 5072178 (1991-12-01), Matsumoto
patent: 5097468 (1992-03-01), Earlie
patent: 5323401 (1994-06-01), Maston
patent: 5341315 (1994-08-01), Niwa et al.

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