Boots – shoes – and leggings
Patent
1997-10-09
1999-01-26
Shah, Alpesh M.
Boots, shoes, and leggings
395562, 36473601, G06F 1576
Patent
active
058647031
ABSTRACT:
The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, a first vector register and a second vector register are read from the register file. The present invention then executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The result of the execution is then written into the accumulator. Then, each element in the accumulator is transformed into an N-bit width element and stored into the memory.
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patent: 5758176 (1998-05-01), Agarwal et al.
Hsu Peter
Huffman William A.
Killian Earl A.
Moreton Henry P.
van Hook Timothy
MIPS Technologies Inc.
Shah Alpesh M.
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