Method for providing ESD protection for an integrated circuit

Details Method for providing ESD protection for an integrated circuit Method for providing ESD protection for an integrated circuit

2000-09-07

2001-07-17

Sherry, Michael J. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000, C716S030000

Reexamination Certificate

active

06262873

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to electrostatic discharge (ESD) and electrical overstress (EOS) protection circuitry and more particularly to ESD and EOS protection circuitry for electronic circuits employing multiple power supply rails.
BACKGROUND OF THE INVENTION
Techniques for protecting integrated circuits from large, undesirable current and voltage signals (e.g., ESD, EOS, etc.) are well known, particularly for integrated circuits employing a single power supply rail (hereinafter “power rail”). In single power rail systems, ESD and EOS protection circuitry (hereinafter “ESD circuitry”) need only be provided between a single power rail and a reference power rail such as ground (hereinafter “reference rail”). More recently, multiple power rail applications such as mixed-voltage interface circuitry, dynamic random access memory (DRAM) circuitry and the like have necessitated ESD protection between multiple power rails as well as between each power rail and ground.
Many multiple power rail applications have the additional requirement that power rails must be able to be powered-up or powered-down in any sequence without generating wasteful or harmful voltage or current conditions between the power rails (i.e., a sequence independence or power-up/power-down independence requirement). For example, an interface circuit between a printer and a computer should prevent current flow between the computer and the printer when only one of the computer and the printer is ON.
One conventional technique for providing multiple power rail, sequence independent ESD circuitry is disclosed in commonly assigned U.S. Pat. No. 5,610,791 to Voldman and is described with reference to FIG.
1
. Specifically,
FIG. 1
shows conventional ESD circuitry
101
which comprises a first single-rail ESD circuit
103
a
connected between a first power rail (V
DD1
) and a reference rail (V
SS
) (e.g., ground), a second single-rail ESD circuit
103
b
connected between a second power rail (V
DD2
) and the reference rail (V
SS
), and an inter-rail ESD circuit
105
connected between the first and the second power rails (V
DD1
), (V
DD2
). As described below, each single-rail ESD circuit
103
a
,
103
b
produces a low impedance path between the single-rail ESD circuit's respective power rail and the reference rail (V
SS
) in response to an ESD impulse on the respective power rail so that the ESD impulse's energy is harmlessly dissipated (i.e., providing “single-rail” ESD protection). Similarly, the inter-rail ESD circuit
105
produces a low impedance path between the first and the second power rails (V
DD1
), (V
DD2
) in response to an ESD impulse applied therebetween so that the ESD impulse's energy is harmlessly dissipated (i.e., providing “inter-rail” ESD protection). A control connection
107
within the inter-rail ESD circuit
105
prevents the inter-rail ESD circuit
105
from dissipating current between the first and the second power rails (V
DD1
), (V
DD2
) in a sequence independent manner (as described below).
The first single-rail ESD circuit
103
a
comprises a plurality of p-channel metal-oxide-semiconductor field-effect-transistors (PFETs), specifically a first PFET
109
and a second PFET
111
, and a first capacitor
113
. The first PFET
109
has a source lead “S” and well lead “W” connected to the first power rail (V
DD1
), a gate lead “G” connected to the reference rail (V
SS
), and a drain lead “D” connected to the gate lead “G” of the second PFET
111
and to the reference rail (V
SS
) via the first capacitor
113
. The second PFET
111
has a source lead “S” and a well lead “W” connected to the first power rail (V
DD1
) and a drain lead “D” connected to the reference rail (V
SS
). The second single-rail ESD circuit
103
b
comprises a third PFET
115
, a fourth PFET
117
and a second capacitor
119
similarly interconnected between the second power rail (V
DD2
) and the reference rail (V
SS
).
In operation, with the gate lead of the first PFET
109
connected to the reference rail (V
SS
) (e.g., ground), the first PFET
109
is ON and behaves as a resistor connected between the gate lead of the second PFET
111
and the first power rail (V
DD1
). The first PFET
109
and the first capacitor
113
thus form an RC discriminator (e.g., a low pass filter) such that the first capacitor
113
can charge quickly enough to track low frequency (e.g., D.C.) voltage changes on the first power rail (V
DD1
). Accordingly, absent a high frequency change in voltage on the first power rail (V
DD1
), the voltage present on the gate of the second PFET
111
and the voltage present on the source of the second PFET
111
remain approximately equal (e.g., V
GS
=0), and the second PFET
111
remains OFF. However, with the channel resistance R of the first PFET
109
and the capacitance C of the first capacitor
113
properly chosen, the first capacitor
113
is unable to charge quickly enough to track the high frequency voltage changes on the first power rail (V
DD1
) due to an ESD impulse. Accordingly, when an ESD impulse is present on the first power rail (V
DD1
), the voltage present on the gate of the second PFET
111
initially remains unchanged (as the first capacitor
113
charges toward the ESD impulse's voltage) while the source and the well of the second PFET
111
track the voltage of the ESD impulse. The gate-to-source voltage of the second PFET
111
, therefore, exceeds the second PFET
111
's threshold voltage and the second PFET
111
turns ON. With the second PFET
111
ON, a low impedance path is created between the first power rail (V
DD1
) and the reference rail (V
SS
).
The second PFET
111
remains ON until the first capacitor
113
charges to a voltage sufficient to turn OFF the second PFET
111
or until the ESD impulse is dissipated, whichever occurs first. If the charging time for the first capacitor
113
is sufficiently long (as set by the RC time constant of the current path to the first capacitor
113
, which is set by the first PFET
109
and the first capacitor
113
), the second PFET
111
will remain ON long enough for the ESD impulse to be harmlessly dissipated (e.g., to ground). The second single-rail ESD circuit
103
b
behaves identically with respect to the second power rail (V
DD2
).
The inter-rail ESD circuit
105
comprises a fifth PFET
121
and a first PNP transistor
123
. The fifth PFET
121
has a gate lead “G” connected to the second power rail (V
DD2
), a source lead “S” connected to the first power rail (V
DD1
) and a drain lead “D” connected to the well “W” of the fifth PFET
121
and to the well “W” (e.g., the base) of the first PNP transistor
123
via the control connection
107
(forming a node
107
′). The first PNP transistor
123
has a collector lead “C” connected to the first power rail (V
DD1
) and an emitter lead “E” connected to the second power rail (V
DD2
). For reasons described below, the fifth PFET
121
is sized much smaller than the first PNP transistor
123
and the first PNP transistor
123
is symmetrically doped.
When an ESD impulse is present across the first and the second power rails (V
DD1
), (V
DD2
), the fifth PFET
121
has little affect on the response of the first PNP transistor
123
(due to its small size relative to the first PNP transistor
123
). For instance, with an ESD impulse induced on the first power rail (V
DD1
) relative to the second power rail (V
DD2
), the collector of the first PNP transistor
123
is pulled high rapidly via the ESD impulse and the first PNP transistor
123
's collector-base junction is forward biased while the first PNP transistor
123
's emitter-base junction is reverse biased. The first PNP transistor
123
thereby is turned ON, current flows from the first power rail (V
DD1
) to the second power rail (V
DD2
) and the ESD impulse is harmlessly dissipated. Base current is “forced” through the fifth PFET
121
during dissipation of the ESD impulse.
Similarly, with an ESD impulse induced on the second power rail (V
DD2

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