Fishing – trapping – and vermin destroying
Patent
1987-11-13
1989-07-25
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 64, 437 67, 437 78, 437 90, 437 86, 437228, 437239, 437974, 437978, 437 72, 148DIG50, H01L 2176
Patent
active
048513660
ABSTRACT:
A novel process and structure is taught which provides discrete semiconductor islands located in a semiconductor substrate, the islands being electrically isolated from each other. Certain of these islands, in addition to being electrically isolated from other islands, are also electrically isolated from the substrate. Yet other ones of these islands are electrically isolated from other islands, but are electrically connected to the substrate. In accordance with the teachings of this invention, a substrate is used and a layer of electrical insulation is formed over only a portion of the surface of the substrate. Grooves are then formed to serve as vertical isolation regions. The grooves are filled with a non-conductive material, or covered with a layer of insulation on their sides and bottom, and filled with any convenient material, such as polycrystalline silicon. A second semiconductor substrate is then bonded to the first, and serves as the ultimate substrate of the finished device. The surface of the first substrate opposite said second substrate is etched to the vertical grooves, thereby providing a surface having vertical grooves serving as vertical isolation. The insulation layer formed on the surface of the first substrate serves as isolation between the islands and second substrate, a while the absence of such insulation layer causes certain other islands to be electrically connected to the second substrate.
REFERENCES:
patent: 3423255 (1969-01-01), Joyce
patent: 3738883 (1973-06-01), Bean et al.
patent: 3832247 (1974-08-01), Saddler et al.
patent: 3913121 (1973-10-01), Youmans et al.
patent: 4004046 (1977-01-01), Price
patent: 4056414 (1977-11-01), Kopp
patent: 4501060 (1985-02-01), Frye et al.
Brassington et al., IEEE Trans. on Electron Devices, "A Comparison of Fine-Dimension Silicon-on-Sapphire and Bulk-Silicon Complementary MOS Devices and Circuits" (Sep. 1985), pp. 1858-1867.
Partridge, IEDM 86, "The Current Status of Silicon-on-Insulator Technologies-A Comparison" (1986), pp. 428-430.
Ohashi et al., IEDM 86, "Improved Dielectrically Isolated Device Integration by Silicon-Wafer Direct Bonding (SDB) Technique" (1986), pp. 210-213.
Nakagawa et al., IEDM 86, "1800V Bipolar-Mode MOSFETs: A First Application of Silicon Wafer Direct Bonding (SDB) Technique to a Power Device" (1986).
Frye et al., J. Electrochem. Soc., "A Field-Assisted Bonding Process for Silicon Dielectric Isolation" (Aug. 1986), pp. 1673-1677.
Ohata and Izumita, IEEE 1987 Custom Integrated Circuits Conferences, "Dielectrically Isolated Intelligent Power Switch" (1987), pp. 443-446.
Caserza Steven F.
Hearn Brian E.
Pawlikowski Beverly A.
Siliconix incorporated
LandOfFree
Method for providing dielectrically isolated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for providing dielectrically isolated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for providing dielectrically isolated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2358048