Method for providing both level-sensitive and edge-sensitive int

Details Method for providing both level-sensitive and edge-sensitive int Method for providing both level-sensitive and edge-sensitive int

1996-02-12

1998-12-08

An, Meng-Ai T.

Boots, shoes, and leggings

395735, 395737, 364940, 364240, G06F 1300

Patent

active

058482776

ABSTRACT:
A method or protocol for generating an Interrupt Signal for communication between a peripheral device and a host processor having either a level-sensitive or an edge-sensitive interrupt detector. After receiving an active interrupt request, and after confirming that the Chip Select signal is released, the interrupt signal is transitioned to an active level. After receiving an active Chip Select signal and multiple Clock pulses from the host as confirmation of receipt of the Interrupt Signal, the Interrupt Signal is transitioned to its inactive state. If the interrupt request is still pending, and when the Chip Select signal is released, then the Interrupt Signal is again made active. Maintaining the active level for the Interrupt Signal until the confirmation is returned from the host will activate level-sensitive detectors, while edge-sensitive detectors in the host will be activated by the multiple transitions ocurring if the host does not service the interrupt request in the peripheral.

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