Patent
1994-09-30
1998-02-10
Harvey, Jack B.
395611, 395612, 395800, G06F 1300
Patent
active
057179166
ABSTRACT:
A fully associative cache memory has a finite state machine which creates and maintains a linked list structure within the cache. This linked list structure allows the fully associative cache memory to be implemented in a structure other than a complex FIFO arrangement, as is typically required by systems of the prior art.
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patent: 4499539 (1985-02-01), Vosacek
patent: 4574346 (1986-03-01), Hartung
patent: 4636946 (1987-01-01), Hartung et al.
patent: 5390318 (1995-02-01), Ramakrishnan et al.
DeCegma, "Parallel Processing Architectures and VLSI Hardware"pp. 318-331 Prentic-Hall Inc. Englewood Cliffs, New Jersey (1989).
Darbe Valerie
Harvey Jack B.
Moy Jeffrey D.
VLSI Technology Inc.
Weiss Harry M.
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