Method for providing a low temperature curable gallium alloy...

Metal treatment – Process of modifying or maintaining internal physical... – Producing or treating layered – bonded – welded – or...

Reexamination Certificate

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C148S400000, C420S555000, C228S037000, C438S637000

Reexamination Certificate

active

06554923

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to microchip packaging, and more particularly, to a system and method for providing a ternary gallium alloy that may be used for via-hole filling and for providing interconnects for microelectronic high density packaging interconnections.
BACKGROUND OF THE INVENTION
With advancements in technology, new requirements have developed for microchip packaging. Among theses new requirements are a need for higher circuit density, fine line resolution, mixed signal circuitry, resistance to higher temperatures and resistance to severe environmental effects.
Very large-scale integrated circuits (VLSI) use multilevel circuit interconnections to provide high density and reliability in a compact structure. During fabrication, a layer of metallization is deposited on a silicon wafer and conductors are etch defined. A layer of dielectric is then deposited and windows, or via-holes, are etched through the dielectric to connect points on the metallization. The next layer of metallized conductors is then applied to form interconnections.
One of the major contributors to effective microchip packaging, and therefore responsible for satisfying the new requirements, is via-hole filling. Conductive polymer pastes are widely used as via-hole filling materials for microelectronic interconnections. Unfortunately, these polymer-based pastes have low electrical and thermal conductivity, which contributes to higher electrical via resistance. In addition, the polymer produces shrinkage voids during curing of host polymers. These shrinkage voids result in poor yield and interfacial adhesion to via-hole side walls.
Metallic amalgams have been used as interconnect material in the microelectronics packaging industry. The amalgams are mechanically alloyed mixtures of a liquid metal with other metallic powders formed at room temperature. As known in the art, the first stage of the amalgamation is the wetting of the powdered metal particles by the liquid metal and is achieved by an amalgamation process such as, but not limited to, tumbling or mixing with a mortar and pestle. The second step is the mechanical alloying process where the liquid metal penetrates through the skin of the metal particles thereby forming inter-metallic compounds. The primary processing requirements for mechanical alloying are to provide reasonably long shelf life and good fluidity to allow wetting of the bonding materials. Unfortunately, current alloy compositions have a short shelf life of only a few hours at ambient temperature before they harden.
BRIEF SUMMARY OF THE INVENTION
In light of the foregoing, the invention is a system and method for providing a gallium alloy based via-hole fill that expands during curing, resulting in better bonding to via side walls and better yields of throughhole interconnections for multi-chip module substrates.
Generally, the present invention can be viewed as providing a method for via-hole filling. In this regard, the method can be broadly summarized by the following steps: melting gallium metal; mixing the melted gallium metal with a measured amount of copper and nickel, thereby creating a gallium alloy; drilling via-holes within a substrate; filling the via-holes with gallium alloy; removing excess gallium alloy from the substrate; and curing the substrate having the filled via-holes.
The invention has numerous advantages, a few of which are delineated hereafter as examples. Note that the embodiments of the invention, which are described herein, possess one or more, but not necessarily all, of the advantages set out hereafter. One advantage of the invention is that it provides for easy printing at room temperature.
Another advantage is that it provides an improved via-hole fill that bonds to via side walls and expands with curing.
Another advantage is that it provides better yield for through hole interconnections.
Other features and advantages of the present invention will become apparent to one of reasonable skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention as described by the claims.


REFERENCES:
patent: 4398975 (1983-08-01), Ohasawa et al.
patent: 5053195 (1991-10-01), MacKay
patent: 5061442 (1991-10-01), Ozimek
patent: 5225157 (1993-07-01), McKay
patent: 5427895 (1995-06-01), Magnuson et al.
patent: 5496619 (1996-03-01), Itagaki et al.
patent: 5672913 (1997-09-01), Baldwin et al.
Deshmukh et al., “Gallium Alloy Interconnects for Flip-Chip Assembly Applications,” IEEE Electronic Components and Technology Conference, 1996, pp. 1143-1150.
Baldwin, Daniel F.; Deshmukh, Rajan D.; and Hau, Christine S., “Gallium Alloy Interconnects For Flip-Chip Assembly Applications.” 1996 Electronic Components and Technology Conference, pp. 1143-1150.
Bhattacharya, S. K. and Baldwin, D. F., “A low temperature processable ternary gallium alloy via filling application in microelectronic packaging.” Journal of Materials Science: Materials in Electronics 11 (2000), pp. 653-656.
Bhattacharya, Swapan K. and Baldwin, Daniel F., “Gallium alloy breakthrough for via-filling application.” Advanced Packaging, Sep. 2000, pp. 61-64.
C. MacKay and G. Schuldt “Applications of Amalgams in Micoelectronic Bonding”, Proceedings of the 7th Electronics Materials and Processing Congress, Cambridge, Massachusetts, Aug. 1992, pp. 141-147.
T. Dolbear, “Liquid metal pastes for thermal connections”, Proceedings of the 7th Electronics Materials and Processing Congress, Cambridge, Massachusetts, Aug. 1992, pp. 133-139.
D. Baldwin, R. Deshmukh, and C. Hau, “Preparation and properties of gallium for use as microelectronic interconnect materials”, The International Journal of Microcircuits and Electronic Packaging, vol. 19, No. 1, 1996, pp. 37-45.
C. MacKay, “Amalgams as alternative bonding materials”, International Electronic Packaging Society Conference, San Diego, California, 1989, pp. 1244-1259.
A. Dang, I.C. Ume, and S. Bhattacharya, “A study on warpage of flexible SS substrates for large area MCM-D packaging”, ASME J. Electronic Packaging, vol. 122, Jun. 2000, pp. 87-91.
A. Dang, I.C. Ume, and S. Bhattacharya, “Measurement of Dynamic warpage During Thermal Cycling of Dielectric Coated SS Substrates”, ASME J. Electronic Packaging, vol. 122, Jun. 2000, pp. 77-85.
Swapan K. Bhattacharya, I. Charles Ume, and Daniel F. Baldwin, “Warpage of Conductive Gallium Alloy Via-Filled Stainless Steel Substrates for Large Area Microelectronic Packaging”, International Journal of Microcircuits and Electronic Packaging, vol. 23, No. 3, 2000, pp. 309-319.
Y. Polosky and I.C. Ume, “Thermoelastic Modeling of a PWB with Simulated Circuit Traces Subjected to IR Reflow Soldering with Experimental Validation”, ASME J. Electronic Packaging, vol. 121, No. 4, pp. 263-270, 1999.
Y. Polosky, W. Southerlin and I.C. Ume, “A comparison of PWB warpage due to simulated infrared and wave soldering processes”, IEEE, CPMT, Part C (accepted for publication), IEEE Trans. on Electronics Packaging Manufacturing, vol. 23, No.3, Jul. 2000.
T. Martin, C. Yeh and I.C. Ume, “Measuring of thermally induced warpage in printed wiring boards”, Manufacturing Processes and Materials Challenges in Microelectronics Packaging, ASME Appl. Mech. Div., vol. 131, pp. 43-47, 1991.
C. Yeh, I.C. Ume, R. Fulton, K. Wyatt and J. Stafford, “Correlation of analytical and experimental approaches to determine thermally induced PWB warpage”, IEEE Transactions on Components, Hybrids and Manufacturing Technology, vol. 16, pp. 986-995, 1993.
C. Yeh, K. Banerjee, T. Martin, C. Umeagukwu, J. Stafford and K. Wyatt, “Experimental and analytical investigation of thermally induced warpage for printed wiring boards”, Proceedings IEEE Electronic Components Conference, Atlanta, pp. 382-387, 1991.
I. Zewi, I. Daniel and J. Gotro, “Residual stresses and warpage in circuit board composite laminates”, Proceedings 1985 SEM Fall Conference on Experimental Mechanics: Transducer Technology for Physical Measu

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