Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1997-08-07
1999-03-16
Powell, William
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438655, 438630, H01L 2100
Patent
active
058830103
ABSTRACT:
Problems forming silicided and nonsilicided structures on the same silicon substrate are overcome utilizing a spacer oxide masking technique. A protective spacer oxide layer is deposited over the entire silicon substrate surface, and a silicide exclusion photoresist mask is selectively developed to permit etching of the spacer oxide layer in unmasked regions where silicides are expected to be formed. Areas of silicon substrate revealed by etching of the spacer oxide layer are exposed to silicide-forming metals, and these silicide-forming metals react with the silicon substrate to produce silicides. Spacer oxide remaining in masked regions prevents formation of silicides in those regions.
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patent: 4742025 (1988-05-01), Ohyu et al.
patent: 5342798 (1994-08-01), Huang
patent: 5352631 (1994-10-01), Sitaram et al.
patent: 5413969 (1995-05-01), Huang
patent: 5750438 (1998-05-01), Hsue et al.
Merrill Richard B.
Pierce John M.
Teng C. S.
National Semiconductor Corporation
Powell William
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