Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2003-04-18
2004-11-23
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S058000, C361S111000, C361S220000
Reexamination Certificate
active
06822840
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method to protect MOS components and the apparatus thereof. In particular, the present invention relates to a method to protect MOS components from antenna effect and the apparatus thereof.
2. Description of the Related Art
During plasma etching, damaging induced by plasma to the MOS component are referred to as plasma charging damaging, or antenna effect. Due to the uneven distribution characteristics of charges in plasma, charges are accumulated on the conductors (such as: polysilicon or aluminum alloys) with large surface areas or long sides. The charges generate an electric field on the gate oxide layer of the MOS component. When enough charges are collected, the electric field across the gate oxide layer changes the properties of the MOS component. More severe damage may occur if the current is high enough to pass through the gate oxide layer.
FIG. 1
shows a conventional circuit design using a diode to reduce the antenna affect. In
FIG. 1
, T
1
is a MOS component in an integrated circuit (IC), the substrate (or bulk) B of the MOS is coupled to its own source, or to a fixed power rail (VDD or VSS). The diode D
1
has its anode coupled to the substrate of the IC. It is assumed that the conductive line L
1
connected with the gate of the MOS component T
1
has a very large surface area or periphery length. Due to the plasma characteristics, a large amount of charges is accumulated on the conductive line L
1
, causing the antenna affect (as the antenna shown in FIG.
1
).
If the accumulated charges are negative charges, the diode D
1
provides a discharge path to release the negative charges to the substrate of the IC, preventing damaging made to the gate oxide layer of the MOS component T
1
. However, when the accumulated charges are positive charges, no discharge path exists. The electric field across the gate oxide layer thus degrades the layer. Moreover, the large stray capacitance of the diode D
1
compromises the operating rate of the IC circuit, resulting in slower operating speeds.
FIG. 2
shows a conventional circuit design using a transmission gate to reduce the antenna effect. In
FIG. 2
, the conductive line L
2
connected to the gate of the MOS component T
2
has very a large area or is very long. Due to the plasma distribution characteristics, large amounts of charges are accumulated on the conductive line L
2
, causing the antenna effect (as the antenna shown in FIG.
2
). Herein, T
2
is the MOS component of a IC circuit with its substrate B connected to the source or a fixed power rail (VDD or VSS).
To reduce the antenna effect, a transmission gate is placed in the IC circuit in FIG.
2
and coupled with the gate of the MOS component T
2
. In the NMOS transistor NT of the transmission gate, the gate and the substrate are respectively coupled to the nodes VDD and VSS. In the PMOS transistor PT of the transmission gate, the gate and the substrate are respectively coupled to the nodes VSS and VDD. Irrespective of whether the accumulated charges in the antenna effect are of either of the bias polarities, they are discharged through the parasitic diodes between the source/drain and the substrate of the NMOS transistor NT (or PMOS transistor PT) to prevent the MOS component T
2
from degradation.
Because the transmission gate is located on the path for controlling the gate of the MOS component T
2
, and the transmission gate has parasitic capacitor C and resistance R, the RC constant will lead to the delay of the control signal sent to the gate of T
2
and compromise the operating rate of the MOS component T
2
. To enhance the operating rate of the MOS component T
2
, resistance R is expected to be reduced. The easiest way to reduce the resistance R is to cut the channel length or increase the channel width of the transmission gate. However, by doing so, the capacitance C is simultaneously increased. Therefore, it is awkward to reduce the antenna effect by adjusting the R and C values according to the configuration in FIG.
2
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an apparatus for protecting an MOS component from the antenna effect. The apparatus comprises a bypass PMOS transistor whose gate, source and substrate are coupled to a first voltage node, and that, when positive charges are accumulated on the gate of the MOS component due to antenna effect, conveys the positive charges to the first voltage node to prevent them from entering and damaging the MOS component; and a bypass NMOS transistor, whose gate, source and substrate are coupled to a second voltage node, and that, when negative charges are accumulated on the gate of the MOS component due to the antenna effect, conveys the negative charges to the second voltage node to prevent them from entering and damaging the MOS component.
Another object of the present invention is to provide a method for protecting an MOS component from antenna effect. The method comprises disposal, between a first voltage node and the MOS component, of a bypass PMOS transistor, the gate, source and substrate of which are coupled to the first voltage node and the drain of which is coupled to the gate of the MOS component; and disposal, between a second voltage node and the MOS component, of a second bypass NMOS transistor, the gate, source and substrate of which are coupled to the second voltage node and the drain of which is coupled to the gate of the MOS component.
When positive charges accumulate on the gate of the MOS component due to the antenna effect, the bypass PMOS transistor conveys the positive charges to the first voltage node to prevent them from entering and damaging the MOS component. When the negative charges accumulate on the gate of the MOS component due to the antenna effect, the bypass NMOS transistor conveys the negative charges to the second voltage node to prevent them from entering and damaging the MOS component.
REFERENCES:
patent: 5817577 (1998-10-01), Ko
patent: 6317306 (2001-11-01), Chen et al.
patent: 6365939 (2002-04-01), Noguchi
patent: 6537883 (2003-03-01), Chen et al.
Birch & Stewart Kolasch & Birch, LLP
Jackson Stephen W.
Taiwan Semiconductor Manufacturing Co. Ltd.
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