Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-07-10
2004-11-09
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C438S396000
Reexamination Certificate
active
06815222
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for production of a semiconductor device. More particularly, the present invention relates to a method for production of a semiconductor device with capacitive elements formed therein.
The recent trend in electronic machines and equipment is toward size reduction and weight reduction. Under this state, semiconductor devices used in electronic machines and equipment are required to carry out many functions individually, and hence each semiconductor device has various electronic elements formed therein. Among these electronic elements is a capacitive element or capacitor of MIM (Metal Insulator Metal) structure.
A conventional technology to form a capacitor of MIM structure in a semiconductor device includes a step of sequentially forming on a semiconductor substrate a lower electrode film, a dielectric film, and an upper electrode film, a step of forming a resist pattern conforming to the desired figure of the capacitor, and a step of performing etching.
FIGS. 13A
to
13
C are sectional views showing step by step the conventional method for producing a semiconductor device with a capacitive element formed therein.
FIG. 13A
is to sequentially form on a semiconductor substrate an insulating film, a lower electrode film, a dielectric film, and an upper electrode film.
FIG. 13B
, which follows
FIG. 13A
, is to form a resist pattern on the upper electrode film which becomes the upper electrode later.
FIG. 13C
, which follows
FIG. 13B
, is to form the upper electrode pattern and the dielectric pattern by etching.
FIG. 13A
shows that a semiconductor substrate
20
is sequentially coated with an insulating film
21
of silicon oxide (SiO
2
) or the like, a lower electrode film
22
, a dielectric film
23
, and an upper electrode film
24
.
FIG. 13B
shows that the upper electrode film
24
is coated with a photoresist, which is made into a photoresist pattern
25
later.
FIG. 13C
shows that the upper electrode film
24
and the dielectric film
23
simultaneously undergo etching such as RIE (reactive ion etching) through the photoresist pattern
25
as a mask. Thus, there are formed an upper electrode pattern
24
a
and a dielectric pattern
23
a.
The conventional technology mentioned above has, however, the disadvantage of causing overetching. Overetching is a phenomenon that etching to work the upper electrode film
24
and the dielectric film
23
undesirably affects the lower electrode film
22
. The result of overetching is sputtering, which is a phenomenon that the constituents of the lower electrode film
22
are driven out and scattered, as indicated by the arrow A in FIG.
13
C. Scattered particles deposit on the side walls of the upper electrode pattern
24
a
and the dielectric pattern
23
a
, and the upper surface of the lower electrode film
22
. They form the conductive deposit
26
which short-circuits an upper electrode pattern
24
a
to the lower electrode film
22
.
SUMMARY OF THE INVENTION
The present invention was completed in view of the foregoing. It is an object of the present invention to provide a method for production of a semiconductor device which avoids a short circuit between the upper and lower electrodes in its step of forming capacitive elements.
According to an aspect of the present invention, there is provided a method for production of a semiconductor device having capacitive elements including:
a step of forming a lower electrode film on an insulating film formed on a substrate;
a step of forming a dielectric film on the lower electrode film;
a step of forming an upper electrode film on the dielectric film;
a step of forming a pattern to form an upper electrode pattern of the capacitive elements on the upper electrode film;
a step of etching the upper electrode film by using the pattern to form the upper electrode pattern as a mask;
a step of forming a pattern to form a dielectric pattern for the capacitive element such that it includes the upper electrode pattern; and
a step of etching the dielectric film by using the pattern to form the dielectric pattern as a mask.
According to the production method mentioned above, the resist pattern to form the dielectric pattern is so formed as to cover the upper electrode pattern. Therefore, this resist pattern protects the upper electrode from deposit of the constituents of the lower electrode film which are scattered by sputtering action when the dielectric film undergoes etching.
The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements denoted by like reference symbols.
REFERENCES:
patent: 6075691 (2000-06-01), Duenas et al.
patent: 6483142 (2002-11-01), Hsue et al.
patent: 6524868 (2003-02-01), Choi et al.
patent: 6533948 (2003-03-01), Kato et al.
patent: 6576526 (2003-06-01), Kai et al.
Depke Robert J.
Holland & Knight LLP
Nguyen Thanh
Sony Corporation
LandOfFree
Method for protecting capacitive elements during production... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for protecting capacitive elements during production..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for protecting capacitive elements during production... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3342418