Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Patent
1995-05-30
1997-07-01
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
257661, 257662, 257663, 257666, 505191, 505237, 505847, 505900, H01L 2906, H01L 3900
Patent
active
056441436
ABSTRACT:
Various techniques for forming superconductive lines are described whereby superconductive lines can be formed by stamping, etching, polishing, or by rendering selected areas of a superconductive film (layer) non-superconductive. The superconductive material can be "perfected" (or optimized) after it is formed into lines (traces). In one embodiment, trenches are etched in a substrate, the trenches are filled with superconductive material, and any excess superconductive material overfilling the trenches is removed, such as by polishing. In another embodiment, superconductive lines are formed by rendering selected areas of a superconductive layer (i.e., areas other than the desired superconductive lines) non-superconductive by "damaging" the superconductive material by laser beam heating, or by ion implantation. Superconductive lines formed according to the invention can be used to protect semiconductor devices (e.g., transistor structures) from over-current or overheating conditions such as those caused by CMOS latch-up. Current density limits and/or thermal limits of superconductors are employed to cause a superconductive trace to become non-superconductive when these limits are exceeded.
REFERENCES:
patent: 4837609 (1989-06-01), Gurvitch et al.
patent: 4953005 (1990-08-01), Carlson et al.
patent: 5227361 (1993-07-01), Yamazaki
patent: 5304539 (1994-04-01), Allen et al.
Pasch Nicholas F.
Rostoker Michael D.
Schneider Mark
Schneider William C.
Yee Abraham
Crane Sara W.
LSI Logic Corporation
Weiss Howard
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