Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-04-09
2004-09-07
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S185220, C365S185240, C365S189090, C365S226000
Reexamination Certificate
active
06788579
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for programming nonvolatile memory cells with a program and verify algorithm in which the amplitude of the programming pulses increases in staircase fashion with a variable slope.
2. Description of the Related Art
As is known, the most widely used programming methods for nonvolatile memory cells are based upon program and verify algorithms. This approach can be applied both to programming by injection of hot electrons from the channel and to programming via Fowler-Nordheim tunnelling, and is particularly indicated whenever a high programming precision is required, as in the case of multilevel storage.
Programming of a nonvolatile memory cell is normally performed by means of a sequence of programming steps interspersed with verification steps in which the state of the memory cell is verified. In this connection, see, for example, G. Torelli, P. Lupi, “An Improved Method for Programming a Word-erasable EEPROM,”
Alta Frequenza,
Vol. LII, n. 6, November/December 1983, pp. 487-494.
In particular, during the programming steps a programming voltage is applied to the gate terminal of the memory cell, the amplitude of which is increased by a constant amount at each programming step, and the sequence is continued until the threshold voltage of the memory cell, which was initially at a low value, reaches the desired value.
In order for the programmed level of the threshold voltage to be increased by the same amount at each step, with a constant temporal duration for the programming steps, it is necessary to apply increasingly higher programming voltages to the gate terminal of the memory cell being programmed. If at each programming step the voltage V
G
on the gate terminal is increased by a constant amount &Dgr;V
G
=V
G,(i+1)
−V
G,i
(where i designates a generic programming step) and if the temporal duration of the programming phase at each individual step is sufficient, in steady-state conditions a constant increment &Dgr;V
T
=V
T,(i+1)
−V
T,i
is obtained of the threshold voltage for each programming step.
In this connection, see, for example, C. Calligaro, A. Manstretta, P. Rolandi, G. Torelli, “Technological and Design Constraints for Multilevel Flash Memories,”
Proc.
3
rd IEEE Int. Con.f on Electronics, Circuits and Systems (ICECS)
, October 1996, pp. 1005-1008, and T. S. Jung, et al., “A 17-mm2 3.3 V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications,”
IEEE J. Solid-State Circuits,
vol. 31, No. 11, 1996, pp. 1575-1583, in which programming methods are described for programming multilevel memories with a pulsed voltage, the amplitude of which increases in staircase fashion with a constant slope, i.e., in which the programming voltage is constituted by a succession of programming pulses where the voltage difference between one pulse and the preceding one is constant.
FIG. 1
shows a graph presented in the above-mentioned paper “Technological and Design Constraints for Multilevel Flash Memories” and representing the linear relationship existing between the threshold voltage of a memory cell and the programming voltage applied to the gate terminal of the memory cell, when said programming voltage presents a pulsed pattern the amplitude of which increases in staircase fashion.
In particular,
FIG. 1
shows various programming curves obtained with &Dgr;V
G
=500 mV, in which appearing on the top horizontal axis is the voltage V
G
applied to the gate terminal of a memory cell, on the bottom horizontal axis is the number of steps, and on the vertical axis is the overall threshold-voltage variation starting from a pre-set initial value (in
FIG. 1
, &Dgr;V
T
designates the overall threshold-voltage variation, whereas in the present text &Dgr;V
T
designates the threshold-voltage variation obtained with a single programming pulse).
When a program and verify algorithm is used, the amplitude of the programmed threshold voltage distributions depends upon the variation of the threshold voltage &Dgr;V
T
obtained at each step. In particular, the programming precision, i.e., the maximum difference between the threshold-voltage value actually obtained and the desired nominal value, depends upon &Dgr;V
T
. For practical purposes, therefore, the programming precision depends upon A V
G
, i.e., upon the increment of the programming voltage at each programming step.
In order to obtain a high programming precision, which is indispensable in multilevel digital storage, it is thus necessary to reduce &Dgr;V
G
as much as possible. In this connection, see, for example, B. Riccò, et al., “Nonvolatile Multilevel Memories for Digital Applications,”
Proceedings of the IEEE,
Vol. 86, No. 12, December 1998, pp. 2399-2421.
Obviously, the higher the number of bits that are to be stored in the individual memory cell, the greater is the programming precision required. If the same range of programmable threshold voltages is available, given the same technological generation, in order to increase by one bit the information content storable in a single cell, it is necessary at least to double the programming precision. For practical purposes, even when the programming precision is doubled, the noise margin between two adjacent distributions of programmed threshold voltages is halved, and hence the programming precision must be further increased in order to obtain an acceptable level of reliability.
FIG. 2
is a qualitative representation of the distributions of programmed threshold voltages for multilevel cells with 2-bit per cell, using a technology currently available in which the range of programmable threshold voltages is fixed between 1 V and 6 V. Also represented in
FIG. 2
are the distributions of threshold voltages that may be obtained in the same voltage range for multilevel cells with 4-bit per cell. Likewise represented in
FIG. 2
, as hatched areas, are the corresponding noise margins.
In this case, even supposing that it is possible to reduce the noise margins by a factor of four, the width of the programmed threshold voltage distributions must be reduced by at least a factor of four.
Reduction in &Dgr;V
G
in order to increase programming precision determines an increase in programming times. To obtain the same overall threshold voltage variation, using programming steps having the same temporal duration, with &Dgr;V
G
halved, twice as much time is required. Returning to the previous example, given the same technology, 4-bit-per-cell programming, as compared to 2-bit-per-cell programming, requires at least four times as long. For this reason, the increase in programming times may prove a limit for the development of multilevel memories with a high number of bits per cell.
In order to reduce the programming time, then, programming methods have been proposed for programming nonvolatile memories with staircase programming voltages, where the amplitude of the steps is not constant, but rather varies according to different modalities.
For example, the U.S. patents U.S. Pat. No. 4,357,685 “Method of Programming an Electrically Alterable Nonvolatile Memory”, and U.S. Pat. No. 5,812,457 “Semiconductor NAND Type Flash Memory with Incremental Step Pulse Programming” describe methods for programming non-multilevel memories, in which the programming voltage is formed by a succession of programming pulses having increasing amplitude or duration, whilst the U.S. Pat. No. 5,257,255 “Method for Programming Programmable Devices by Utilizing Single or Multiple Pulses Varying in Pulse Width and Amplitude” describes a programming method that uses single or multiple pulses having varying amplitude or duration, in which a first train of programming pulses is applied to an electrode of the programmable device and, simultaneously, a second train of programming pulses is applied to a second electrode of the programmable device.
Although the programming methods using staircase programming voltages with varying incremental amplitude between adjacent programmin
Gregori Stefano
Khouri Osama
Micheloni Rino
Pierin Andrea
Torelli Guido
Bennett II Harold H.
Elms Richard
Jorgenson Lisa K.
Luu Pho M.
Seed IP Law Group PLLC
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