Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-02-01
2008-07-08
Mai, Son L (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185240
Reexamination Certificate
active
07397705
ABSTRACT:
A method for operating a charge-trapping multi-level cell (“MLC”) memory array comprises programming a first plurality of charge-trapping sites to a preliminary first-level value, programming a second plurality of charge-trapping sites to a preliminary second-level value, and programming a third plurality of charge-trapping sites to a final third-level value using a first programming scheme. Then, the first plurality of charge-trapping sites is programmed to a final first-level value and the second plurality of charge-trapping sites is programmed to a final second-level value using a second programming scheme.
REFERENCES:
patent: 6011725 (2000-01-01), Eitan et al.
patent: 6320786 (2001-11-01), Chang et al.
patent: 6487114 (2002-11-01), Jong et al.
patent: 6714457 (2004-03-01), Hsu et al.
patent: 6928001 (2005-08-01), Avni et al.
patent: 6937511 (2005-08-01), Hsu et al.
patent: 6981107 (2005-12-01), Lomazzi et al.
patent: 7133317 (2006-11-01), Liao et al.
patent: 7136304 (2006-11-01), Cohen et al.
patent: 7190614 (2007-03-01), Wu
patent: 2006/0146603 (2006-07-01), Kuo et al.
Chen Chung Kuang
Ho Hsin Yi
Huang Chun Jen
Haynes Beffel & Wolfeld LLP
Macronix International Co. Ltd.
Mai Son L
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